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Searched refs:SCLK_UART0_PMU (Results 1 – 11 of 11) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Drockchip,px30-cru.txt61 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Dpx30-cru.h193 #define SCLK_UART0_PMU 6 macro
H A Drk1808-cru.h105 #define SCLK_UART0_PMU 104 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dpx30-cru.h188 #define SCLK_UART0_PMU 6 macro
H A Drk1808-cru.h105 #define SCLK_UART0_PMU 104 macro
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-px30.c941 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
H A Dclk-rk1808.c1100 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk1808.dtsi521 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>;
H A Dpx30.dtsi228 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk1808.dtsi993 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>;
H A Dpx30.dtsi675 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;