| /OK3568_Linux_fs/u-boot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 37 case MPLL: in s5pc100_get_pll_clk()
88 case MPLL: in s5pc110_get_pll_clk()
108 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()
207 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); in get_pclkd1()
237 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 126 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()
196 case MPLL: in exynos4_get_pll_clk()
226 case MPLL: in exynos4x12_get_pll_clk()
257 case MPLL: in exynos5_get_pll_clk()
280 if (pllreg == MPLL || pllreg == BPLL) { in exynos5_get_pll_clk()
284 case MPLL: in exynos5_get_pll_clk()
315 case MPLL: in exynos542x_get_pll_clk()
438 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()
529 sclk = exynos542x_get_pll_clk(MPLL); in exynos542x_get_periph_rate()
653 sclk = get_pll_clk(MPLL); in exynos4_get_pwm_clk()
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clk.h | 13 #define MPLL 1 macro
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| /OK3568_Linux_fs/u-boot/include/dt-bindings/clock/ |
| H A D | microchip,clock.h | 14 #define MPLL 2 macro
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-s3c2410.c | 109 ALIAS(MPLL, NULL, "mpll"),
155 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
221 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
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| H A D | clk-s3c2443.c | 148 ALIAS(MPLL, NULL, "mpll"),
182 PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
234 PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
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| H A D | clk-s3c2412.c | 101 PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
155 ALIAS(MPLL, NULL, "mpll"),
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| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 22 #define MPLL 2 macro
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| H A D | s3c2412.h | 22 #define MPLL 2 macro
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| H A D | s3c2443.h | 26 #define MPLL 7 macro
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 12 #define MPLL 1 macro
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| /OK3568_Linux_fs/u-boot/arch/mips/mach-pic32/ |
| H A D | cpu.c | 158 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); in soc_clk_dump()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/ |
| H A D | mdio-mux-meson-g12a.txt | 14 * "clkin1" : SoC 50MHz MPLL
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | exynos5422-odroid-core.dtsi | 41 /* derived from 532MHz MPLL */
133 /* derived from 532MHz MPLL */
181 /* derived from 532MHz MPLL */
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | mvebu-core-clock.txt | 38 3 = mpll (MPLL Clock)
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| /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/video/ |
| H A D | exynos-fb.txt | 55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
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| /OK3568_Linux_fs/u-boot/drivers/clk/ |
| H A D | clk_pic32.c | 357 case MPLL: in pic32_get_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/ingenic/ |
| H A D | jz4780-cgu.c | 301 .pll = DEF_PLL(MPLL),
|