1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree binding constants clock controllers of Samsung S3C2443 and later. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Let each exported clock get a unique index, which is used on DT-enabled 13*4882a593Smuzhiyun * platforms to lookup the clock from a clock specifier. These indices are 14*4882a593Smuzhiyun * therefore considered an ABI and so must not be changed. This implies 15*4882a593Smuzhiyun * that new clocks should be added either in free spaces between clock groups 16*4882a593Smuzhiyun * or at the end. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Core clocks. */ 20*4882a593Smuzhiyun #define MSYSCLK 1 21*4882a593Smuzhiyun #define ESYSCLK 2 22*4882a593Smuzhiyun #define ARMDIV 3 23*4882a593Smuzhiyun #define ARMCLK 4 24*4882a593Smuzhiyun #define HCLK 5 25*4882a593Smuzhiyun #define PCLK 6 26*4882a593Smuzhiyun #define MPLL 7 27*4882a593Smuzhiyun #define EPLL 8 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Special clocks */ 30*4882a593Smuzhiyun #define SCLK_HSSPI0 16 31*4882a593Smuzhiyun #define SCLK_FIMD 17 32*4882a593Smuzhiyun #define SCLK_I2S0 18 33*4882a593Smuzhiyun #define SCLK_I2S1 19 34*4882a593Smuzhiyun #define SCLK_HSMMC1 20 35*4882a593Smuzhiyun #define SCLK_HSMMC_EXT 21 36*4882a593Smuzhiyun #define SCLK_CAM 22 37*4882a593Smuzhiyun #define SCLK_UART 23 38*4882a593Smuzhiyun #define SCLK_USBH 24 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Muxes */ 41*4882a593Smuzhiyun #define MUX_HSSPI0 32 42*4882a593Smuzhiyun #define MUX_HSSPI1 33 43*4882a593Smuzhiyun #define MUX_HSMMC0 34 44*4882a593Smuzhiyun #define MUX_HSMMC1 35 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* hclk-gates */ 47*4882a593Smuzhiyun #define HCLK_DMA0 48 48*4882a593Smuzhiyun #define HCLK_DMA1 49 49*4882a593Smuzhiyun #define HCLK_DMA2 50 50*4882a593Smuzhiyun #define HCLK_DMA3 51 51*4882a593Smuzhiyun #define HCLK_DMA4 52 52*4882a593Smuzhiyun #define HCLK_DMA5 53 53*4882a593Smuzhiyun #define HCLK_DMA6 54 54*4882a593Smuzhiyun #define HCLK_DMA7 55 55*4882a593Smuzhiyun #define HCLK_CAM 56 56*4882a593Smuzhiyun #define HCLK_LCD 57 57*4882a593Smuzhiyun #define HCLK_USBH 58 58*4882a593Smuzhiyun #define HCLK_USBD 59 59*4882a593Smuzhiyun #define HCLK_IROM 60 60*4882a593Smuzhiyun #define HCLK_HSMMC0 61 61*4882a593Smuzhiyun #define HCLK_HSMMC1 62 62*4882a593Smuzhiyun #define HCLK_CFC 63 63*4882a593Smuzhiyun #define HCLK_SSMC 64 64*4882a593Smuzhiyun #define HCLK_DRAM 65 65*4882a593Smuzhiyun #define HCLK_2D 66 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* pclk-gates */ 68*4882a593Smuzhiyun #define PCLK_UART0 72 69*4882a593Smuzhiyun #define PCLK_UART1 73 70*4882a593Smuzhiyun #define PCLK_UART2 74 71*4882a593Smuzhiyun #define PCLK_UART3 75 72*4882a593Smuzhiyun #define PCLK_I2C0 76 73*4882a593Smuzhiyun #define PCLK_SDI 77 74*4882a593Smuzhiyun #define PCLK_SPI0 78 75*4882a593Smuzhiyun #define PCLK_ADC 79 76*4882a593Smuzhiyun #define PCLK_AC97 80 77*4882a593Smuzhiyun #define PCLK_I2S0 81 78*4882a593Smuzhiyun #define PCLK_PWM 82 79*4882a593Smuzhiyun #define PCLK_WDT 83 80*4882a593Smuzhiyun #define PCLK_RTC 84 81*4882a593Smuzhiyun #define PCLK_GPIO 85 82*4882a593Smuzhiyun #define PCLK_SPI1 86 83*4882a593Smuzhiyun #define PCLK_CHIPID 87 84*4882a593Smuzhiyun #define PCLK_I2C1 88 85*4882a593Smuzhiyun #define PCLK_I2S1 89 86*4882a593Smuzhiyun #define PCLK_PCM 90 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Total number of clocks. */ 89*4882a593Smuzhiyun #define NR_CLKS (PCLK_PCM + 1) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ 92