1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree binding constants clock controllers of Samsung S3C2412. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Let each exported clock get a unique index, which is used on DT-enabled 13*4882a593Smuzhiyun * platforms to lookup the clock from a clock specifier. These indices are 14*4882a593Smuzhiyun * therefore considered an ABI and so must not be changed. This implies 15*4882a593Smuzhiyun * that new clocks should be added either in free spaces between clock groups 16*4882a593Smuzhiyun * or at the end. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Core clocks. */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* id 1 is reserved */ 22*4882a593Smuzhiyun #define MPLL 2 23*4882a593Smuzhiyun #define UPLL 3 24*4882a593Smuzhiyun #define MDIVCLK 4 25*4882a593Smuzhiyun #define MSYSCLK 5 26*4882a593Smuzhiyun #define USYSCLK 6 27*4882a593Smuzhiyun #define HCLK 7 28*4882a593Smuzhiyun #define PCLK 8 29*4882a593Smuzhiyun #define ARMDIV 9 30*4882a593Smuzhiyun #define ARMCLK 10 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Special clocks */ 34*4882a593Smuzhiyun #define SCLK_CAM 16 35*4882a593Smuzhiyun #define SCLK_UART 17 36*4882a593Smuzhiyun #define SCLK_I2S 18 37*4882a593Smuzhiyun #define SCLK_USBD 19 38*4882a593Smuzhiyun #define SCLK_USBH 20 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* pclk-gates */ 41*4882a593Smuzhiyun #define PCLK_WDT 32 42*4882a593Smuzhiyun #define PCLK_SPI 33 43*4882a593Smuzhiyun #define PCLK_I2S 34 44*4882a593Smuzhiyun #define PCLK_I2C 35 45*4882a593Smuzhiyun #define PCLK_ADC 36 46*4882a593Smuzhiyun #define PCLK_RTC 37 47*4882a593Smuzhiyun #define PCLK_GPIO 38 48*4882a593Smuzhiyun #define PCLK_UART2 39 49*4882a593Smuzhiyun #define PCLK_UART1 40 50*4882a593Smuzhiyun #define PCLK_UART0 41 51*4882a593Smuzhiyun #define PCLK_SDI 42 52*4882a593Smuzhiyun #define PCLK_PWM 43 53*4882a593Smuzhiyun #define PCLK_USBD 44 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* hclk-gates */ 56*4882a593Smuzhiyun #define HCLK_HALF 48 57*4882a593Smuzhiyun #define HCLK_X2 49 58*4882a593Smuzhiyun #define HCLK_SDRAM 50 59*4882a593Smuzhiyun #define HCLK_USBH 51 60*4882a593Smuzhiyun #define HCLK_LCD 52 61*4882a593Smuzhiyun #define HCLK_NAND 53 62*4882a593Smuzhiyun #define HCLK_DMA3 54 63*4882a593Smuzhiyun #define HCLK_DMA2 55 64*4882a593Smuzhiyun #define HCLK_DMA1 56 65*4882a593Smuzhiyun #define HCLK_DMA0 57 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Total number of clocks. */ 68*4882a593Smuzhiyun #define NR_CLKS (HCLK_DMA0 + 1) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */ 71