1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree binding constants clock controllers of Samsung S3C2410 and later. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Let each exported clock get a unique index, which is used on DT-enabled 13*4882a593Smuzhiyun * platforms to lookup the clock from a clock specifier. These indices are 14*4882a593Smuzhiyun * therefore considered an ABI and so must not be changed. This implies 15*4882a593Smuzhiyun * that new clocks should be added either in free spaces between clock groups 16*4882a593Smuzhiyun * or at the end. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Core clocks. */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* id 1 is reserved */ 22*4882a593Smuzhiyun #define MPLL 2 23*4882a593Smuzhiyun #define UPLL 3 24*4882a593Smuzhiyun #define FCLK 4 25*4882a593Smuzhiyun #define HCLK 5 26*4882a593Smuzhiyun #define PCLK 6 27*4882a593Smuzhiyun #define UCLK 7 28*4882a593Smuzhiyun #define ARMCLK 8 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* pclk-gates */ 31*4882a593Smuzhiyun #define PCLK_UART0 16 32*4882a593Smuzhiyun #define PCLK_UART1 17 33*4882a593Smuzhiyun #define PCLK_UART2 18 34*4882a593Smuzhiyun #define PCLK_I2C 19 35*4882a593Smuzhiyun #define PCLK_SDI 20 36*4882a593Smuzhiyun #define PCLK_SPI 21 37*4882a593Smuzhiyun #define PCLK_ADC 22 38*4882a593Smuzhiyun #define PCLK_AC97 23 39*4882a593Smuzhiyun #define PCLK_I2S 24 40*4882a593Smuzhiyun #define PCLK_PWM 25 41*4882a593Smuzhiyun #define PCLK_RTC 26 42*4882a593Smuzhiyun #define PCLK_GPIO 27 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* hclk-gates */ 46*4882a593Smuzhiyun #define HCLK_LCD 32 47*4882a593Smuzhiyun #define HCLK_USBH 33 48*4882a593Smuzhiyun #define HCLK_USBD 34 49*4882a593Smuzhiyun #define HCLK_NAND 35 50*4882a593Smuzhiyun #define HCLK_CAM 36 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CAMIF 40 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Total number of clocks. */ 57*4882a593Smuzhiyun #define NR_CLKS (CAMIF + 1) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ 60