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/OK3568_Linux_fs/external/xserver/hw/xfree86/common/
H A Dextramodes30 # 640x360 59.32 Hz (CVT 0.23M9-R) hsync: 22.19 kHz; pclk: 17.75 MHz
33 # 640x360 59.84 Hz (CVT 0.23M9) hsync: 22.50 kHz; pclk: 18.00 MHz
36 # 720x405 58.99 Hz (CVT 0.29M9-R) hsync: 24.72 kHz; pclk: 21.75 MHz
39 # 720x405 59.51 Hz (CVT 0.29M9) hsync: 25.11 kHz; pclk: 22.50 MHz
42 # 864x486 59.57 Hz (CVT 0.42M9-R) hsync: 29.79 kHz; pclk: 30.50 MHz
45 # 864x486 59.92 Hz (CVT 0.42M9) hsync: 30.32 kHz; pclk: 32.50 MHz
48 # 960x540 59.82 Hz (CVT 0.52M9-R) hsync: 33.26 kHz; pclk: 37.25 MHz
51 # 960x540 59.63 Hz (CVT 0.52M9) hsync: 33.51 kHz; pclk: 40.75 MHz
54 # 1024x576 59.82 Hz (CVT 0.59M9-R) hsync: 35.47 kHz; pclk: 42.00 MHz
57 # 1024x576 59.90 Hz (CVT 0.59M9) hsync: 35.88 kHz; pclk: 46.50 MHz
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-sched-energy.dtsi29 210 129 /* 408MHz */
30 308 184 /* 600MHz */
31 419 246 /* 816MHz */
32 518 335 /* 1008MHz */
33 617 428 /* 1200MHz */
34 728 573 /* 1416MHz */
35 827 724 /* 1608MHz */
36 925 900 /* 1800MHz */
37 1024 1108 /* 1992MHz */
67 210 129 /* 408MHz */
[all …]
H A Drk3588j.dtsi11 * The Max frequency is 1296MHz in default normal mode.
12 * The Max frequency is 1704MHz in overdrive mode,
24 * The Max frequency is 1608MHz in default normal mode.
25 * The Max frequency is 2016MHz in overdrive mode,
36 * The Max frequency is 1608MHz in default normal mode.
37 * The Max frequency is 2016MHz in overdrive mode,
48 * The Max frequency is 700MHz in default normal mode.
49 * The Max frequency is 850MHz in overdrive mode,
59 * The Max frequency is 800MHz in default normal mode.
60 * The Max frequency is 950MHz in overdrive mode,
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h78 #define MHz 1000000 macro
80 #define OSC_HZ (24*MHz)
81 #define APLL_HZ (600*MHz)
82 #define GPLL_HZ (800 * MHz)
83 #define CPLL_HZ (384*MHz)
84 #define NPLL_HZ (600 * MHz)
85 #define PPLL_HZ (676*MHz)
87 #define PMU_PCLK_HZ (48*MHz)
89 #define ACLKM_CORE_HZ (300*MHz)
90 #define ATCLK_CORE_HZ (300*MHz)
[all …]
H A Dcru_rv1126.h12 #define MHz 1000000 macro
14 #define OSC_HZ (24 * MHz)
17 #define APLL_HZ (1008 * MHz)
19 #define APLL_HZ (816 * MHz)
21 #define GPLL_HZ (1188 * MHz)
22 #define CPLL_HZ (500 * MHz)
23 #define HPLL_HZ (1400 * MHz)
24 #define PCLK_PDPMU_HZ (100 * MHz)
26 #define ACLK_PDBUS_HZ (396 * MHz)
28 #define ACLK_PDBUS_HZ (500 * MHz)
[all …]
H A Dcru_px30.h11 #define MHz 1000000 macro
13 #define OSC_HZ (24 * MHz)
15 #define APLL_HZ (600 * MHz)
16 #define GPLL_HZ (1200 * MHz)
17 #define NPLL_HZ (1188 * MHz)
18 #define ACLK_BUS_HZ (200 * MHz)
19 #define HCLK_BUS_HZ (150 * MHz)
20 #define PCLK_BUS_HZ (100 * MHz)
21 #define ACLK_PERI_HZ (200 * MHz)
22 #define HCLK_PERI_HZ (150 * MHz)
[all …]
H A Dcru_rk322x.h11 #define MHz 1000 * 1000 macro
12 #define OSC_HZ (24 * MHz)
13 #define APLL_HZ (600 * MHz)
14 #define GPLL_HZ (1200 * MHz)
15 #define CPLL_HZ (500 * MHz)
16 #define ACLK_BUS_HZ (150 * MHz)
17 #define ACLK_PERI_HZ (150 * MHz)
H A Dcru_rk3328.h72 #define MHz 1000 * 1000 macro
73 #define OSC_HZ (24 * MHz)
74 #define APLL_HZ (600 * MHz)
76 #define CPLL_HZ (1200 * MHz)
77 #define ACLK_BUS_HZ (150 * MHz)
78 #define ACLK_PERI_HZ (150 * MHz)
79 #define PWM_CLOCK_HZ (74 * MHz)
/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rv1106.c86 rate = 400 * MHz; in rv1106_peri_get_clk()
88 rate = 200 * MHz; in rv1106_peri_get_clk()
90 rate = 100 * MHz; in rv1106_peri_get_clk()
98 rate = 200 * MHz; in rv1106_peri_get_clk()
100 rate = 100 * MHz; in rv1106_peri_get_clk()
102 rate = 50 * MHz; in rv1106_peri_get_clk()
110 rate = 100 * MHz; in rv1106_peri_get_clk()
112 rate = 50 * MHz; in rv1106_peri_get_clk()
120 rate = 300 * MHz; in rv1106_peri_get_clk()
122 rate = 200 * MHz; in rv1106_peri_get_clk()
[all …]
H A Dclk_rk3568.c739 rate = 200 * MHz; in rk3568_bus_get_clk()
741 rate = 150 * MHz; in rk3568_bus_get_clk()
743 rate = 100 * MHz; in rk3568_bus_get_clk()
752 rate = 100 * MHz; in rk3568_bus_get_clk()
754 rate = 75 * MHz; in rk3568_bus_get_clk()
756 rate = 50 * MHz; in rk3568_bus_get_clk()
775 if (rate == 200 * MHz) in rk3568_bus_set_clk()
777 else if (rate == 150 * MHz) in rk3568_bus_set_clk()
779 else if (rate == 100 * MHz) in rk3568_bus_set_clk()
789 if (rate == 100 * MHz) in rk3568_bus_set_clk()
[all …]
H A Dclk_rk3588.c161 rate = 702 * MHz; in rk3588_center_get_clk()
163 rate = 396 * MHz; in rk3588_center_get_clk()
165 rate = 200 * MHz; in rk3588_center_get_clk()
174 rate = 500 * MHz; in rk3588_center_get_clk()
176 rate = 250 * MHz; in rk3588_center_get_clk()
178 rate = 100 * MHz; in rk3588_center_get_clk()
187 rate = 396 * MHz; in rk3588_center_get_clk()
189 rate = 200 * MHz; in rk3588_center_get_clk()
191 rate = 100 * MHz; in rk3588_center_get_clk()
200 rate = 200 * MHz; in rk3588_center_get_clk()
[all …]
/OK3568_Linux_fs/external/xserver/debian/patches/
H A D001_fedora_extramodes.patch18 +# 1152x864 @ 60.00 Hz (GTF) hsync: 53.70 kHz; pclk: 81.62 MHz
21 +# 1152x864 @ 70.00 Hz (GTF) hsync: 63.00 kHz; pclk: 96.77 MHz
24 +# 1152x864 @ 75.00 Hz (GTF) hsync: 67.65 kHz; pclk: 104.99 MHz
27 +# 1152x864 @ 85.00 Hz (GTF) hsync: 77.10 kHz; pclk: 119.65 MHz
33 +# 1152x864 @ 100.00 Hz (GTF) hsync: 91.50 kHz; pclk: 143.47 MHz
36 +# 1360x768 59.96 Hz (CVT) hsync: 47.37 kHz; pclk: 72.00 MHz
39 +# 1360x768 59.80 Hz (CVT) hsync: 47.72 kHz; pclk: 84.75 MHz
45 +# 1400x1050 @ 70.00 Hz (GTF) hsync: 76.51 kHz; pclk: 145.06 MHz
51 +# 1400x1050 @ 85.00 Hz (GTF) hsync: 93.76 kHz; pclk: 179.26 MHz
54 +# 1440x900 @ 60.00 Hz (CVT) field rate 59.89 Hz; hsync: 55.93 kHz; pclk: 106.50 MHz
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Ddvb-pll.c74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
121 .max = 900 * MHz,
138 .min = 174 * MHz,
139 .max = 862 * MHz,
154 .min = 174 * MHz,
155 .max = 862 * MHz,
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.Heterogeneous-SoCs90 CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
91 DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
92 DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
93 CCB:666.667 MHz,
94 DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
95 CPRI:600 MHz
96 MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
97 FMAN1: 666.667 MHz
98 QMAN: 333.333 MHz
/OK3568_Linux_fs/kernel/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst34 - 1.712 MHz
42 - 5 MHz
50 - 6 MHz
58 - 7 MHz
66 - 8 MHz
74 - 10 MHz
/OK3568_Linux_fs/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
242 /* Set maximum frequency as 1000MHz */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/OK3568_Linux_fs/buildroot/package/rtl_433/
H A DConfig.in9 for the 433.92 MHz, 868 MHz (SRD), 315 MHz, 345 MHz, and 915
10 MHz ISM bands.
/OK3568_Linux_fs/buildroot/package/cache-calibrator/
H A D0001-Fix-conflicting-round-function.patch29 @@ -890,16 +890,16 @@ void plotCache(cacheInfo *cache, lng **result, lng MHz, char *fn, FILE *fp, l…
39 fprintf(fp, "%s'%1.3g' %ld", s, (dbl)(y * MHz) / 1000.0, y);
43 - if (!delay) z = (dbl)round(CYperIt(cache->latency1[l] - delay)) * 1000.0 / (dbl)MHz;
44 - else z = (dbl)round(CYperIt(cache->latency2[l] - delay)) * 1000.0 / (dbl)MHz;
45 + if (!delay) z = (dbl)lng_round(CYperIt(cache->latency1[l] - delay)) * 1000.0 / (dbl)MHz;
46 + else z = (dbl)lng_round(CYperIt(cache->latency2[l] - delay)) * 1000.0 / (dbl)MHz;
50 @@ -986,16 +986,16 @@ void plotTLB(TLBinfo *TLB, lng **result, lng MHz, char *fn, FILE *fp, lng del…
60 fprintf(fp, "%s'%1.3g' %ld", s, (dbl)(y * MHz) / 1000.0, y);
64 - if (!delay) z = (dbl)round(CYperIt(TLB->latency1[l] - delay)) * 1000.0 / (dbl)MHz;
65 - else z = (dbl)round(CYperIt(TLB->latency2[l] - delay)) * 1000.0 / (dbl)MHz;
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/sm750fb/
H A Dddk750_chip.c9 #define MHz(x) ((x) * 1000000) macro
40 return MHz(130); in get_mxclk_freq()
101 if (frequency > MHz(336)) in set_memory_clock()
102 frequency = MHz(336); in set_memory_clock()
153 if (frequency > MHz(190)) in set_master_clock()
154 frequency = MHz(190); in set_master_clock()
240 set_chip_clock(MHz((unsigned int)p_init_param->chip_clock)); in ddk750_init_hw()
243 set_memory_clock(MHz(p_init_param->mem_clock)); in ddk750_init_hw()
246 set_master_clock(MHz(p_init_param->master_clock)); in ddk750_init_hw()
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
121 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
130 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
146 /* TIMER0 runs directly on the 25MHz chrystal */
152 /* TIMER1 runs @ 1MHz */
158 /* TIMER2 runs @ 1MHz */
294 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
/OK3568_Linux_fs/kernel/drivers/media/firewire/
H A Dfiredtv-fe.c173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
/OK3568_Linux_fs/u-boot/board/freescale/t102xqds/
H A DREADME114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
115 - Software programmable in 1 MHz increments from 1-200 MHz.
118 - 100 MHz, 125 MHz and 156.25 MHz options.
119 - Spread-spectrum option for 100 MHz.
196 0x6F 100MHz 125MHz 1101
197 0xD6 100MHz 100MHz 1111
198 0x99 156.25MHz 100MHz 1011
204 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
205 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
206 Bin3: 1000MHz 1600MT/s 400MHz 500MHz

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