Searched refs:CHSCCDR_CLK_SEL_LDB_DI0 (Results 1 – 15 of 15) sorted by relevance
450 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_b850v3()494 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_bx50v3()
455 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in enable_lvds()543 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in enable_spi_display()
566 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()568 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
516 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()518 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
172 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
408 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_clock()
359 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
650 setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()652 CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
481 (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
407 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
596 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
781 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
511 #define CHSCCDR_CLK_SEL_LDB_DI0 3 macro
718 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
456 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()