Searched refs:CG_SPLL_FUNC_CNTL_2 (Results 1 – 22 of 22) sorted by relevance
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/ |
| H A D | rv740d.h | 34 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
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| H A D | rv730d.h | 37 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
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| H A D | rv770.c | 1145 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_set_clk_bypass_mode()
1148 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
1157 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
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| H A D | rv740_dpm.c | 291 RREG32(CG_SPLL_FUNC_CNTL_2); in rv740_read_clock_registers()
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| H A D | rv730_dpm.c | 204 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
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| H A D | rv770d.h | 100 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
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| H A D | nid.h | 547 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
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| H A D | sid.h | 94 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
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| H A D | cikd.h | 257 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 macro
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| H A D | si.c | 3995 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
3997 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4005 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
4007 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
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| H A D | evergreend.h | 82 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
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| H A D | rv770_dpm.c | 1523 RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_read_clock_registers()
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| H A D | ni_dpm.c | 1185 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in ni_read_clock_registers()
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| H A D | si_dpm.c | 3556 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()
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| H A D | ci_dpm.c | 1862 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); in ci_read_clock_registers()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | si.c | 1228 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
1230 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
1238 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
1240 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
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| H A D | sid.h | 95 #define CG_SPLL_FUNC_CNTL_2 0x181 macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | fiji_smumgr.c | 1348 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, in fiji_populate_smc_acpi_level()
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| H A D | iceland_smumgr.c | 1466 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); in iceland_populate_smc_acpi_level()
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| H A D | ci_smumgr.c | 1419 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); in ci_populate_smc_acpi_level()
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| H A D | tonga_smumgr.c | 1214 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, in tonga_populate_smc_acpi_level()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/ |
| H A D | si_dpm.c | 4012 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()
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