1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef RV730_H 24*4882a593Smuzhiyun #define RV730_H 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CG_SPLL_FUNC_CNTL 0x600 27*4882a593Smuzhiyun #define SPLL_RESET (1 << 0) 28*4882a593Smuzhiyun #define SPLL_SLEEP (1 << 1) 29*4882a593Smuzhiyun #define SPLL_DIVEN (1 << 2) 30*4882a593Smuzhiyun #define SPLL_BYPASS_EN (1 << 3) 31*4882a593Smuzhiyun #define SPLL_REF_DIV(x) ((x) << 4) 32*4882a593Smuzhiyun #define SPLL_REF_DIV_MASK (0x3f << 4) 33*4882a593Smuzhiyun #define SPLL_HILEN(x) ((x) << 12) 34*4882a593Smuzhiyun #define SPLL_HILEN_MASK (0xf << 12) 35*4882a593Smuzhiyun #define SPLL_LOLEN(x) ((x) << 16) 36*4882a593Smuzhiyun #define SPLL_LOLEN_MASK (0xf << 16) 37*4882a593Smuzhiyun #define CG_SPLL_FUNC_CNTL_2 0x604 38*4882a593Smuzhiyun #define SCLK_MUX_SEL(x) ((x) << 0) 39*4882a593Smuzhiyun #define SCLK_MUX_SEL_MASK (0x1ff << 0) 40*4882a593Smuzhiyun #define CG_SPLL_FUNC_CNTL_3 0x608 41*4882a593Smuzhiyun #define SPLL_FB_DIV(x) ((x) << 0) 42*4882a593Smuzhiyun #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 43*4882a593Smuzhiyun #define SPLL_DITHEN (1 << 28) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CG_MPLL_FUNC_CNTL 0x624 46*4882a593Smuzhiyun #define MPLL_RESET (1 << 0) 47*4882a593Smuzhiyun #define MPLL_SLEEP (1 << 1) 48*4882a593Smuzhiyun #define MPLL_DIVEN (1 << 2) 49*4882a593Smuzhiyun #define MPLL_BYPASS_EN (1 << 3) 50*4882a593Smuzhiyun #define MPLL_REF_DIV(x) ((x) << 4) 51*4882a593Smuzhiyun #define MPLL_REF_DIV_MASK (0x3f << 4) 52*4882a593Smuzhiyun #define MPLL_HILEN(x) ((x) << 12) 53*4882a593Smuzhiyun #define MPLL_HILEN_MASK (0xf << 12) 54*4882a593Smuzhiyun #define MPLL_LOLEN(x) ((x) << 16) 55*4882a593Smuzhiyun #define MPLL_LOLEN_MASK (0xf << 16) 56*4882a593Smuzhiyun #define CG_MPLL_FUNC_CNTL_2 0x628 57*4882a593Smuzhiyun #define MCLK_MUX_SEL(x) ((x) << 0) 58*4882a593Smuzhiyun #define MCLK_MUX_SEL_MASK (0x1ff << 0) 59*4882a593Smuzhiyun #define CG_MPLL_FUNC_CNTL_3 0x62c 60*4882a593Smuzhiyun #define MPLL_FB_DIV(x) ((x) << 0) 61*4882a593Smuzhiyun #define MPLL_FB_DIV_MASK (0x3ffffff << 0) 62*4882a593Smuzhiyun #define MPLL_DITHEN (1 << 28) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define CG_TCI_MPLL_SPREAD_SPECTRUM 0x634 65*4882a593Smuzhiyun #define CG_TCI_MPLL_SPREAD_SPECTRUM_2 0x638 66*4882a593Smuzhiyun #define GENERAL_PWRMGT 0x63c 67*4882a593Smuzhiyun # define GLOBAL_PWRMGT_EN (1 << 0) 68*4882a593Smuzhiyun # define STATIC_PM_EN (1 << 1) 69*4882a593Smuzhiyun # define THERMAL_PROTECTION_DIS (1 << 2) 70*4882a593Smuzhiyun # define THERMAL_PROTECTION_TYPE (1 << 3) 71*4882a593Smuzhiyun # define ENABLE_GEN2PCIE (1 << 4) 72*4882a593Smuzhiyun # define ENABLE_GEN2XSP (1 << 5) 73*4882a593Smuzhiyun # define SW_SMIO_INDEX(x) ((x) << 6) 74*4882a593Smuzhiyun # define SW_SMIO_INDEX_MASK (3 << 6) 75*4882a593Smuzhiyun # define LOW_VOLT_D2_ACPI (1 << 8) 76*4882a593Smuzhiyun # define LOW_VOLT_D3_ACPI (1 << 9) 77*4882a593Smuzhiyun # define VOLT_PWRMGT_EN (1 << 10) 78*4882a593Smuzhiyun # define BACKBIAS_PAD_EN (1 << 18) 79*4882a593Smuzhiyun # define BACKBIAS_VALUE (1 << 19) 80*4882a593Smuzhiyun # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 81*4882a593Smuzhiyun # define AC_DC_SW (1 << 24) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define SCLK_PWRMGT_CNTL 0x644 84*4882a593Smuzhiyun # define SCLK_PWRMGT_OFF (1 << 0) 85*4882a593Smuzhiyun # define SCLK_LOW_D1 (1 << 1) 86*4882a593Smuzhiyun # define FIR_RESET (1 << 4) 87*4882a593Smuzhiyun # define FIR_FORCE_TREND_SEL (1 << 5) 88*4882a593Smuzhiyun # define FIR_TREND_MODE (1 << 6) 89*4882a593Smuzhiyun # define DYN_GFX_CLK_OFF_EN (1 << 7) 90*4882a593Smuzhiyun # define GFX_CLK_FORCE_ON (1 << 8) 91*4882a593Smuzhiyun # define GFX_CLK_REQUEST_OFF (1 << 9) 92*4882a593Smuzhiyun # define GFX_CLK_FORCE_OFF (1 << 10) 93*4882a593Smuzhiyun # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 94*4882a593Smuzhiyun # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 95*4882a593Smuzhiyun # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define TCI_MCLK_PWRMGT_CNTL 0x648 98*4882a593Smuzhiyun # define MPLL_PWRMGT_OFF (1 << 5) 99*4882a593Smuzhiyun # define DLL_READY (1 << 6) 100*4882a593Smuzhiyun # define MC_INT_CNTL (1 << 7) 101*4882a593Smuzhiyun # define MRDCKA_SLEEP (1 << 8) 102*4882a593Smuzhiyun # define MRDCKB_SLEEP (1 << 9) 103*4882a593Smuzhiyun # define MRDCKC_SLEEP (1 << 10) 104*4882a593Smuzhiyun # define MRDCKD_SLEEP (1 << 11) 105*4882a593Smuzhiyun # define MRDCKE_SLEEP (1 << 12) 106*4882a593Smuzhiyun # define MRDCKF_SLEEP (1 << 13) 107*4882a593Smuzhiyun # define MRDCKG_SLEEP (1 << 14) 108*4882a593Smuzhiyun # define MRDCKH_SLEEP (1 << 15) 109*4882a593Smuzhiyun # define MRDCKA_RESET (1 << 16) 110*4882a593Smuzhiyun # define MRDCKB_RESET (1 << 17) 111*4882a593Smuzhiyun # define MRDCKC_RESET (1 << 18) 112*4882a593Smuzhiyun # define MRDCKD_RESET (1 << 19) 113*4882a593Smuzhiyun # define MRDCKE_RESET (1 << 20) 114*4882a593Smuzhiyun # define MRDCKF_RESET (1 << 21) 115*4882a593Smuzhiyun # define MRDCKG_RESET (1 << 22) 116*4882a593Smuzhiyun # define MRDCKH_RESET (1 << 23) 117*4882a593Smuzhiyun # define DLL_READY_READ (1 << 24) 118*4882a593Smuzhiyun # define USE_DISPLAY_GAP (1 << 25) 119*4882a593Smuzhiyun # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 120*4882a593Smuzhiyun # define MPLL_TURNOFF_D2 (1 << 28) 121*4882a593Smuzhiyun #define TCI_DLL_CNTL 0x64c 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define CG_PG_CNTL 0x858 124*4882a593Smuzhiyun # define PWRGATE_ENABLE (1 << 0) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define CG_AT 0x6d4 127*4882a593Smuzhiyun #define CG_R(x) ((x) << 0) 128*4882a593Smuzhiyun #define CG_R_MASK (0xffff << 0) 129*4882a593Smuzhiyun #define CG_L(x) ((x) << 16) 130*4882a593Smuzhiyun #define CG_L_MASK (0xffff << 16) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define CG_SPLL_SPREAD_SPECTRUM 0x790 133*4882a593Smuzhiyun #define SSEN (1 << 0) 134*4882a593Smuzhiyun #define CLK_S(x) ((x) << 4) 135*4882a593Smuzhiyun #define CLK_S_MASK (0xfff << 4) 136*4882a593Smuzhiyun #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 137*4882a593Smuzhiyun #define CLK_V(x) ((x) << 0) 138*4882a593Smuzhiyun #define CLK_V_MASK (0x3ffffff << 0) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING 0x2774 141*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING2 0x2778 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define MC_ARB_RFSH_RATE 0x27b0 144*4882a593Smuzhiyun #define POWERMODE0(x) ((x) << 0) 145*4882a593Smuzhiyun #define POWERMODE0_MASK (0xff << 0) 146*4882a593Smuzhiyun #define POWERMODE1(x) ((x) << 8) 147*4882a593Smuzhiyun #define POWERMODE1_MASK (0xff << 8) 148*4882a593Smuzhiyun #define POWERMODE2(x) ((x) << 16) 149*4882a593Smuzhiyun #define POWERMODE2_MASK (0xff << 16) 150*4882a593Smuzhiyun #define POWERMODE3(x) ((x) << 24) 151*4882a593Smuzhiyun #define POWERMODE3_MASK (0xff << 24) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING_1 0x27f0 154*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING_2 0x27f4 155*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING_3 0x27f8 156*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING2_1 0x27fc 157*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING2_2 0x2800 158*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING2_3 0x2804 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define MC4_IO_DQ_PAD_CNTL_D0_I0 0x2978 161*4882a593Smuzhiyun #define MC4_IO_DQ_PAD_CNTL_D0_I1 0x297c 162*4882a593Smuzhiyun #define MC4_IO_QS_PAD_CNTL_D0_I0 0x2980 163*4882a593Smuzhiyun #define MC4_IO_QS_PAD_CNTL_D0_I1 0x2984 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #endif 166