1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef RV740_H 24*4882a593Smuzhiyun #define RV740_H 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CG_SPLL_FUNC_CNTL 0x600 27*4882a593Smuzhiyun #define SPLL_RESET (1 << 0) 28*4882a593Smuzhiyun #define SPLL_SLEEP (1 << 1) 29*4882a593Smuzhiyun #define SPLL_BYPASS_EN (1 << 3) 30*4882a593Smuzhiyun #define SPLL_REF_DIV(x) ((x) << 4) 31*4882a593Smuzhiyun #define SPLL_REF_DIV_MASK (0x3f << 4) 32*4882a593Smuzhiyun #define SPLL_PDIV_A(x) ((x) << 20) 33*4882a593Smuzhiyun #define SPLL_PDIV_A_MASK (0x7f << 20) 34*4882a593Smuzhiyun #define CG_SPLL_FUNC_CNTL_2 0x604 35*4882a593Smuzhiyun #define SCLK_MUX_SEL(x) ((x) << 0) 36*4882a593Smuzhiyun #define SCLK_MUX_SEL_MASK (0x1ff << 0) 37*4882a593Smuzhiyun #define CG_SPLL_FUNC_CNTL_3 0x608 38*4882a593Smuzhiyun #define SPLL_FB_DIV(x) ((x) << 0) 39*4882a593Smuzhiyun #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 40*4882a593Smuzhiyun #define SPLL_DITHEN (1 << 28) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define MPLL_CNTL_MODE 0x61c 43*4882a593Smuzhiyun #define SS_SSEN (1 << 24) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MPLL_AD_FUNC_CNTL 0x624 46*4882a593Smuzhiyun #define CLKF(x) ((x) << 0) 47*4882a593Smuzhiyun #define CLKF_MASK (0x7f << 0) 48*4882a593Smuzhiyun #define CLKR(x) ((x) << 7) 49*4882a593Smuzhiyun #define CLKR_MASK (0x1f << 7) 50*4882a593Smuzhiyun #define CLKFRAC(x) ((x) << 12) 51*4882a593Smuzhiyun #define CLKFRAC_MASK (0x1f << 12) 52*4882a593Smuzhiyun #define YCLK_POST_DIV(x) ((x) << 17) 53*4882a593Smuzhiyun #define YCLK_POST_DIV_MASK (3 << 17) 54*4882a593Smuzhiyun #define IBIAS(x) ((x) << 20) 55*4882a593Smuzhiyun #define IBIAS_MASK (0x3ff << 20) 56*4882a593Smuzhiyun #define RESET (1 << 30) 57*4882a593Smuzhiyun #define PDNB (1 << 31) 58*4882a593Smuzhiyun #define MPLL_AD_FUNC_CNTL_2 0x628 59*4882a593Smuzhiyun #define BYPASS (1 << 19) 60*4882a593Smuzhiyun #define BIAS_GEN_PDNB (1 << 24) 61*4882a593Smuzhiyun #define RESET_EN (1 << 25) 62*4882a593Smuzhiyun #define VCO_MODE (1 << 29) 63*4882a593Smuzhiyun #define MPLL_DQ_FUNC_CNTL 0x62c 64*4882a593Smuzhiyun #define MPLL_DQ_FUNC_CNTL_2 0x630 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define MCLK_PWRMGT_CNTL 0x648 67*4882a593Smuzhiyun #define DLL_SPEED(x) ((x) << 0) 68*4882a593Smuzhiyun #define DLL_SPEED_MASK (0x1f << 0) 69*4882a593Smuzhiyun # define MPLL_PWRMGT_OFF (1 << 5) 70*4882a593Smuzhiyun # define DLL_READY (1 << 6) 71*4882a593Smuzhiyun # define MC_INT_CNTL (1 << 7) 72*4882a593Smuzhiyun # define MRDCKA0_SLEEP (1 << 8) 73*4882a593Smuzhiyun # define MRDCKA1_SLEEP (1 << 9) 74*4882a593Smuzhiyun # define MRDCKB0_SLEEP (1 << 10) 75*4882a593Smuzhiyun # define MRDCKB1_SLEEP (1 << 11) 76*4882a593Smuzhiyun # define MRDCKC0_SLEEP (1 << 12) 77*4882a593Smuzhiyun # define MRDCKC1_SLEEP (1 << 13) 78*4882a593Smuzhiyun # define MRDCKD0_SLEEP (1 << 14) 79*4882a593Smuzhiyun # define MRDCKD1_SLEEP (1 << 15) 80*4882a593Smuzhiyun # define MRDCKA0_RESET (1 << 16) 81*4882a593Smuzhiyun # define MRDCKA1_RESET (1 << 17) 82*4882a593Smuzhiyun # define MRDCKB0_RESET (1 << 18) 83*4882a593Smuzhiyun # define MRDCKB1_RESET (1 << 19) 84*4882a593Smuzhiyun # define MRDCKC0_RESET (1 << 20) 85*4882a593Smuzhiyun # define MRDCKC1_RESET (1 << 21) 86*4882a593Smuzhiyun # define MRDCKD0_RESET (1 << 22) 87*4882a593Smuzhiyun # define MRDCKD1_RESET (1 << 23) 88*4882a593Smuzhiyun # define DLL_READY_READ (1 << 24) 89*4882a593Smuzhiyun # define USE_DISPLAY_GAP (1 << 25) 90*4882a593Smuzhiyun # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 91*4882a593Smuzhiyun # define MPLL_TURNOFF_D2 (1 << 28) 92*4882a593Smuzhiyun #define DLL_CNTL 0x64c 93*4882a593Smuzhiyun # define MRDCKA0_BYPASS (1 << 24) 94*4882a593Smuzhiyun # define MRDCKA1_BYPASS (1 << 25) 95*4882a593Smuzhiyun # define MRDCKB0_BYPASS (1 << 26) 96*4882a593Smuzhiyun # define MRDCKB1_BYPASS (1 << 27) 97*4882a593Smuzhiyun # define MRDCKC0_BYPASS (1 << 28) 98*4882a593Smuzhiyun # define MRDCKC1_BYPASS (1 << 29) 99*4882a593Smuzhiyun # define MRDCKD0_BYPASS (1 << 30) 100*4882a593Smuzhiyun # define MRDCKD1_BYPASS (1 << 31) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define CG_SPLL_SPREAD_SPECTRUM 0x790 103*4882a593Smuzhiyun #define SSEN (1 << 0) 104*4882a593Smuzhiyun #define CLK_S(x) ((x) << 4) 105*4882a593Smuzhiyun #define CLK_S_MASK (0xfff << 4) 106*4882a593Smuzhiyun #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 107*4882a593Smuzhiyun #define CLK_V(x) ((x) << 0) 108*4882a593Smuzhiyun #define CLK_V_MASK (0x3ffffff << 0) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define MPLL_SS1 0x85c 111*4882a593Smuzhiyun #define CLKV(x) ((x) << 0) 112*4882a593Smuzhiyun #define CLKV_MASK (0x3ffffff << 0) 113*4882a593Smuzhiyun #define MPLL_SS2 0x860 114*4882a593Smuzhiyun #define CLKS(x) ((x) << 0) 115*4882a593Smuzhiyun #define CLKS_MASK (0xfff << 0) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif 118