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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
[all …]
H A Dnvidia,tegra186-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c2 * (C) Copyright 2010 - 2011
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/apb_misc.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/warmboot.h>
27 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in wb_start() local
38 writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl); in wb_start()
[all …]
H A Dwarmboot.c2 * (C) Copyright 2010 - 2011
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/apb_misc.h>
19 #include <asm/arch-tegra/clk_rst.h>
20 #include <asm/arch-tegra/pmc.h>
21 #include <asm/arch-tegra/fuse.h>
22 #include <asm/arch-tegra/warmboot.h>
128 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in warmboot_save_sdram_params() local
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H A Dcpu.c2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
9 #include <asm/arch/tegra.h>
10 #include <asm/arch-tegra/pmc.h>
15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
18 reg = readl(&pmc->pmc_cntrl); in enable_cpu_power_rail()
20 writel(reg, &pmc->pmc_cntrl); in enable_cpu_power_rail()
47 * if it's a non-zero value. in start_cpu()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/
H A Dap.c2 * (C) Copyright 2010-2015
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra AP (Application Processor) code */
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clock.h>
17 #include <asm/arch-tegra/fuse.h>
18 #include <asm/arch-tegra/pmc.h>
19 #include <asm/arch-tegra/scu.h>
20 #include <asm/arch-tegra/tegra.h>
21 #include <asm/arch-tegra/warmboot.h>
[all …]
H A Dboard2.c5 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/board.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/sys_proto.h>
19 #include <asm/arch-tegra/uart.h>
20 #include <asm/arch-tegra/warmboot.h>
21 #include <asm/arch-tegra/gpu.h>
22 #include <asm/arch-tegra/usb.h>
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H A Dcmd_enterrcm.c7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
19 * http://www.dave-tech.it
25 * SPDX-License-Identifier: GPL-2.0+
29 #include <asm/arch/tegra.h>
30 #include <asm/arch-tegra/pmc.h>
35 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in do_enterrcm() local
40 pmc->pmc_scratch0 = 2; in do_enterrcm()
49 "reset Tegra and enter USB Recovery Mode",
H A Dcpu.c2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/pmc.h>
15 #include <asm/arch-tegra/scu.h>
25 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; in get_num_cpus()
49 * ------------------------------
67 * ------------------------------
85 * ------------------------------
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H A Dboard.c2 * (C) Copyright 2010-2015
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/board.h>
19 #include <asm/arch-tegra/pmc.h>
20 #include <asm/arch-tegra/sys_proto.h>
21 #include <asm/arch-tegra/warmboot.h>
59 * This register reads 0xffffffff in non-secure mode. This register in tegra_cpu_is_non_secure()
62 * non-secure mode. in tegra_cpu_is_non_secure()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/
H A Dcpu.c5 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/tegra.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <asm/arch-tegra/ap.h>
20 /* Tegra124-specific CPU init code */
24 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
28 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ in enable_cpu_power_rail()
35 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), in enable_cpu_power_rail()
38 writel(0x7C830, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
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H A Dpsci.c5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch-tegra/ap.h>
14 #include <asm/arch-tegra/pmc.h>
34 * - configure the Flow Controller in psci_board_init()
35 * - power up the CPUs in psci_board_init()
36 * - wait for the CPUs to hit wfi and be powered down again in psci_board_init()
47 writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr); in psci_board_init()
48 writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr); in psci_board_init()
49 writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr); in psci_board_init()
51 writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); in psci_board_init()
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/OK3568_Linux_fs/kernel/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
36 #include <linux/pinctrl/pinconf-generic.h>
47 #include <soc/tegra/common.h>
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra30/
H A Dcpu.c2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/tegra_i2c.h>
17 /* Tegra30-specific CPU init code */
22 writel(addr, &reg->cmd_addr0); in tegra_i2c_ll_write_addr()
23 writel(config, &reg->cnfg); in tegra_i2c_ll_write_addr()
30 writel(data, &reg->cmd_data1); in tegra_i2c_ll_write_data()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra114/
H A Dcpu.c2 * (C) Copyright 2010-2014
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/pmc.h>
18 /* Tegra114-specific CPU init code */
21 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
27 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ in enable_cpu_power_rail()
32 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), in enable_cpu_power_rail()
36 writel(reg, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-tegra/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
12 #include <linux/clk/tegra.h>
21 #include <soc/tegra/flowctrl.h>
22 #include <soc/tegra/fuse.h>
23 #include <soc/tegra/pmc.h>
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
[all …]
H A Dtegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NVIDIA Tegra SoC device tree board support
11 #include <linux/clk/tegra.h>
12 #include <linux/dma-mapping.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/pmc.h>
35 #include <asm/hardware/cache-l2x0.h>
38 #include <asm/mach-types.h>
50 * Storage for debug-macro.S's state.
53 * kernel is loaded. The data is declared here rather than debug-macro.S so
[all …]
/OK3568_Linux_fs/kernel/drivers/cpuidle/
H A Dcpuidle-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU idle driver for Tegra CPUs
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
15 #define pr_fmt(fmt) "tegra-cpuidle: " fmt
26 #include <linux/clk/tegra.h>
29 #include <soc/tegra/cpuidle.h>
30 #include <soc/tegra/flowctrl.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/irq.h>
33 #include <soc/tegra/pm.h>
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
59 * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
7 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
44 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
[all …]
H A Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
144 pmc {
145 nvidia,pins = "pmc";
[all …]
H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
19 stdout-path = "serial0:115200n8";
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/include/nvif/
H A Dos.h1 /* SPDX-License-Identifier: MIT */
15 #include <linux/i2c-algo-bit.h>
17 #include <linux/io-mapping.h>
35 #include <soc/tegra/fuse.h>
36 #include <soc/tegra/pmc.h>
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.txt4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
12 Tegra's pin configuration nodes act as a container for an arbitrary number of
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
34 Optional subnode-properties:
35 - nvidia,function: A string containing the name of the function to mux to the
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra20-tamonten.dtsi13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
16 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
133 pmc {
134 nvidia,pins = "pmc";
231 "lvs", "pmc";
283 nand-controller@70008000 {
[all …]

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