mach-tegra/tegra30/cpu.c

2  * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
4  * SPDX-License-Identifier:	GPL-2.0
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/tegra_i2c.h>
17 /* Tegra30-specific CPU init code */
22 	writel(addr, &reg->cmd_addr0);  in tegra_i2c_ll_write_addr()
23 	writel(config, &reg->cnfg);  in tegra_i2c_ll_write_addr()
30 	writel(data, &reg->cmd_data1);  in tegra_i2c_ll_write_data()
31 	writel(config, &reg->cnfg);  in tegra_i2c_ll_write_data()
51 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;  in enable_cpu_power_rail()  local
55 	reg = readl(&pmc->pmc_cntrl);  in enable_cpu_power_rail()
57 	writel(reg, &pmc->pmc_cntrl);  in enable_cpu_power_rail()
94 	clrbits_le32(flow->cluster_control, 1 << 0);  in t30_init_clocks()
96 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);  in t30_init_clocks()
102 	writel(val, &clkrst->crc_clk_sys_rate);  in t30_init_clocks()
114 	 * Our high-level clock routines are not available prior to  in t30_init_clocks()
115 	 * relocation. We use the low-level functions which require a  in t30_init_clocks()
116 	 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)  in t30_init_clocks()
134 	writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);  in set_cpu_running()
158 	 *  if it's a non-zero value.  in start_cpu()