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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/
H A Dvirt-v7.c5 * Routines to transition ARMv7 processors from secure into non-secure state
6 * and from non-secure SVC into HYP mode
9 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/secure.h>
20 unsigned int reg; in read_id_pfr1() local
22 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); in read_id_pfr1()
23 return reg; in read_id_pfr1()
37 * encode this). Bail out here since we cannot access this without in get_gicd_base_address()
41 printf("nonsec: PERIPHBASE is above 4 GB, no access.\n"); in get_gicd_base_address()
42 return -1; in get_gicd_base_address()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iommu/
H A Dqcom,iommu.txt3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
17 register group access) and "bus" (required for
18 the IOMMUs underlying bus access).
20 - clocks : Phandles for respective clocks described by
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H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
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H A Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c3 * Author: Chen-Yu Tsai <wens@csie.org>
6 * which was based on code by Carl van Schaik <carl@ok-labs.com>.
8 * SPDX-License-Identifier: GPL-2.0
20 #include <asm/secure.h>
33 * The power clamps are located in the unused space after the per-core
64 u32 reg = ONE_MS * ms; in __mdelay() local
66 cp15_write_cntp_tval(reg); in __mdelay()
72 reg = cp15_read_cntp_ctl(); in __mdelay()
73 } while (!(reg & BIT(2))); in __mdelay()
134 writel((u32)entry, &cpucfg->priv0); in sunxi_set_entry_address()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/nvmem/
H A Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data bindings
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@st.com>
19 - $ref: "nvmem.yaml#"
24 - st,stm32f4-otp
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/OK3568_Linux_fs/u-boot/drivers/crypto/fsl/
H A Djobdesc.c7 * SPDX-License-Identifier: GPL-2.0+
19 * Secure memory run command
21 * @param sec_mem_cmd Secure memory command register
22 * @return cmd_status Secure memory command status register
29 uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); in secmem_set_cmd()
43 * Allocates a partition from secure memory, with the id
44 * equal to partition_num. This will de-allocate the page
46 * full access permissions. The permissions are set before,
47 * running a job descriptor. A memory page of secure RAM
59 uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); in caam_page_alloc()
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/OK3568_Linux_fs/kernel/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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/OK3568_Linux_fs/kernel/Documentation/driver-api/
H A Dvfio.rst2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
10 agnostic framework for exposing direct device access to userspace, in
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
15 access ("device assignment") when configured for the highest possible
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
28 and requires root privileges to access things like PCI configuration
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/OK3568_Linux_fs/u-boot/include/
H A Dfsl_sec.h6 * SPDX-License-Identifier: GPL-2.0+
35 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
112 u32 smpart; /* Secure Memory Partition Parameters */
113 u32 smvid; /* Secure Memory Version ID */
114 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
194 * Scatter Gather Entry - Specifies the the Scatter Gather Format
200 uint32_t addr_lo; /* Memory Address - lo */
201 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
203 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
204 uint32_t addr_lo; /* Memory Address - lo */
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dscu.h5 * SPDX-License-Identifier: GPL-2.0+
17 uint scu_reserved0[12]; /* reserved, offset 10-3C */
18 uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
19 uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
20 uint scu_reserved1[2]; /* reserved, offset 48-4C */
21 uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
22 uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-armada100/
H A Dcpu.h4 …* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.c…
6 * SPDX-License-Identifier: GPL-2.0+
20 u8 pad0[0x08 - 0x00];
25 u8 pad1[0x030 - 0x014 - 4];
27 u8 pad2[0x200 - 0x030 - 4];
29 u8 pad3[0x1000 - 0x200 - 4];
32 u8 pad4[0x1020 - 0x1004 - 4];
50 u8 pad3[0x04C - 0x018 - 4];
60 u8 pad5[0x07C - 0x06C - 4];
62 u8 pad6[0x090 - 0x07C - 4];
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dmarvell,icu.txt2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
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/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-mxc_v2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
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/OK3568_Linux_fs/kernel/drivers/perf/
H A Darm_pmu_platform.c1 // SPDX-License-Identifier: GPL-2.0
31 int ret = -ENODEV; in probe_current_pmu()
35 for (; info->init != NULL; info++) { in probe_current_pmu()
36 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
38 ret = info->init(pmu); in probe_current_pmu()
49 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
51 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
55 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
56 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
63 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
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/OK3568_Linux_fs/kernel/drivers/iommu/
H A Dipmmu-vmsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-iommu.h>
12 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
30 #include <asm/dma-iommu.h>
33 #define arm_iommu_attach_device(...) -ENODEV
39 #define IPMMU_CTX_INVALID -1
96 /* -----------------------------------------------------------------------------
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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/OK3568_Linux_fs/kernel/drivers/hwtracing/coresight/
H A Dcoresight-etm4x.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
12 #include "coresight-priv.h"
16 * 0x000 - 0x2FC: Trace registers
17 * 0x300 - 0x314: Management registers
18 * 0x318 - 0xEFC: Trace registers
20 * 0xFA0 - 0xFA4: Trace registers
21 * 0xFA8 - 0xFFC: Management registers
23 /* Trace registers (0x000-0x2FC) */
49 #define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */
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/OK3568_Linux_fs/kernel/arch/xtensa/include/asm/
H A Dthread_info.h2 * include/asm-xtensa/thread_info.h
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
24 * low level task data that entry.S needs immediate access to
25 * - this struct should fit entirely inside of one cache line
26 * - this struct shares the supervisor stack pages
27 * - if the contents of this structure are changed, the assembly constants
51 unsigned long status; /* thread-synchronous flags */
73 * macros/functions for gaining access to the thread information structure
99 #define GET_THREAD_INFO(reg,sp) \ argument
100 extui reg, sp, 0, CURRENT_SHIFT; \
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/OK3568_Linux_fs/kernel/drivers/staging/wfx/
H A Dfwio.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
92 return -ENOMEM; in sram_write_dma_safe()
111 wdev->pdata.file_fw, keyset_chip); in get_firmware()
112 ret = firmware_request_nowarn(fw, filename, wdev->dev); in get_firmware()
114 dev_info(wdev->dev, "can't load %s, falling back to %s.sec\n", in get_firmware()
115 filename, wdev->pdata.file_fw); in get_firmware()
117 wdev->pdata.file_fw); in get_firmware()
118 ret = request_firmware(fw, filename, wdev->dev); in get_firmware()
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/OK3568_Linux_fs/kernel/drivers/mailbox/
H A Dti-msgmgr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
21 #include <linux/soc/ti/ti-msgmgr.h>
23 #define Q_DATA_OFFSET(proxy, queue, reg) \ argument
24 ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4))
29 #define SPROXY_THREAD_DATA_OFFSET(tid, reg) \ argument
30 (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4)
40 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
52 * struct ti_msgmgr_desc - Description of message manager integration
62 * @valid_queues: List of Valid queues that the processor can access
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/OK3568_Linux_fs/kernel/drivers/crypto/caam/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interconnect/
H A Dfsl,imx8m-noc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
17 ("Global Programmers View") but not all. Access to this area might be denied
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 handles memory requests for 40-bit virtual addresses from internal clients
21 available for video and other secure applications, as well as DRAM ECC for
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
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/OK3568_Linux_fs/kernel/drivers/irqchip/
H A Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
27 #include <linux/irqchip/arm-gic-common.h>
28 #include <linux/irqchip/arm-gic-v3.h>
29 #include <linux/irqchip/irq-partition-percpu.h>
38 #include "irq-gic-common.h"
62 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
66 * When security is enabled, non-secure priority values from the (re)distributor
70 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
76 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
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