1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010,2011 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SCU_H_ 9*4882a593Smuzhiyun #define _SCU_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* ARM Snoop Control Unit (SCU) registers */ 12*4882a593Smuzhiyun struct scu_ctlr { 13*4882a593Smuzhiyun uint scu_ctrl; /* SCU Control Register, offset 00 */ 14*4882a593Smuzhiyun uint scu_cfg; /* SCU Config Register, offset 04 */ 15*4882a593Smuzhiyun uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ 16*4882a593Smuzhiyun uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ 17*4882a593Smuzhiyun uint scu_reserved0[12]; /* reserved, offset 10-3C */ 18*4882a593Smuzhiyun uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ 19*4882a593Smuzhiyun uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ 20*4882a593Smuzhiyun uint scu_reserved1[2]; /* reserved, offset 48-4C */ 21*4882a593Smuzhiyun uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ 22*4882a593Smuzhiyun uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define SCU_CTRL_ENABLE (1 << 0) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #endif /* SCU_H */ 28