1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #define pr_fmt(fmt) "GICv3: " fmt
8
9 #include <linux/acpi.h>
10 #include <linux/cpu.h>
11 #include <linux/cpu_pm.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/percpu.h>
19 #include <linux/refcount.h>
20 #include <linux/slab.h>
21 #include <linux/syscore_ops.h>
22 #include <linux/wakeup_reason.h>
23 #include <trace/hooks/gic_v3.h>
24
25
26 #include <linux/irqchip.h>
27 #include <linux/irqchip/arm-gic-common.h>
28 #include <linux/irqchip/arm-gic-v3.h>
29 #include <linux/irqchip/irq-partition-percpu.h>
30
31 #include <asm/cputype.h>
32 #include <asm/exception.h>
33 #include <asm/smp_plat.h>
34 #include <asm/virt.h>
35
36 #include <trace/hooks/gic.h>
37
38 #include "irq-gic-common.h"
39
40 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
41
42 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
43 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
44
45 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
46
47 struct redist_region {
48 void __iomem *redist_base;
49 phys_addr_t phys_base;
50 bool single_redist;
51 };
52
53 static struct gic_chip_data gic_data __read_mostly;
54 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
55
56 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
57 #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
58 #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
59
60 /*
61 * The behaviours of RPR and PMR registers differ depending on the value of
62 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
63 * distributor and redistributors depends on whether security is enabled in the
64 * GIC.
65 *
66 * When security is enabled, non-secure priority values from the (re)distributor
67 * are presented to the GIC CPUIF as follow:
68 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
69 *
70 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
71 * EL1 are subject to a similar operation thus matching the priorities presented
72 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
73 * these values are unchanched by the GIC.
74 *
75 * see GICv3/GICv4 Architecture Specification (IHI0069D):
76 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
77 * priorities.
78 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
79 * interrupt.
80 */
81 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
82
83 /*
84 * Global static key controlling whether an update to PMR allowing more
85 * interrupts requires to be propagated to the redistributor (DSB SY).
86 * And this needs to be exported for modules to be able to enable
87 * interrupts...
88 */
89 DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
90 EXPORT_SYMBOL(gic_pmr_sync);
91
92 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
93 EXPORT_SYMBOL(gic_nonsecure_priorities);
94
95 /*
96 * When the Non-secure world has access to group 0 interrupts (as a
97 * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
98 * return the Distributor's view of the interrupt priority.
99 *
100 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
101 * written by software is moved to the Non-secure range by the Distributor.
102 *
103 * If both are true (which is when gic_nonsecure_priorities gets enabled),
104 * we need to shift down the priority programmed by software to match it
105 * against the value returned by ICC_RPR_EL1.
106 */
107 #define GICD_INT_RPR_PRI(priority) \
108 ({ \
109 u32 __priority = (priority); \
110 if (static_branch_unlikely(&gic_nonsecure_priorities)) \
111 __priority = 0x80 | (__priority >> 1); \
112 \
113 __priority; \
114 })
115
116 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
117 static refcount_t *ppi_nmi_refs;
118
119 static struct gic_kvm_info gic_v3_kvm_info;
120 static DEFINE_PER_CPU(bool, has_rss);
121
122 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
123 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
124 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
125 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
126
127 /* Our default, arbitrary priority value. Linux only uses one anyway. */
128 #define DEFAULT_PMR_VALUE 0xf0
129
130 enum gic_intid_range {
131 SGI_RANGE,
132 PPI_RANGE,
133 SPI_RANGE,
134 EPPI_RANGE,
135 ESPI_RANGE,
136 LPI_RANGE,
137 __INVALID_RANGE__
138 };
139
__get_intid_range(irq_hw_number_t hwirq)140 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
141 {
142 switch (hwirq) {
143 case 0 ... 15:
144 return SGI_RANGE;
145 case 16 ... 31:
146 return PPI_RANGE;
147 case 32 ... 1019:
148 return SPI_RANGE;
149 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
150 return EPPI_RANGE;
151 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
152 return ESPI_RANGE;
153 case 8192 ... GENMASK(23, 0):
154 return LPI_RANGE;
155 default:
156 return __INVALID_RANGE__;
157 }
158 }
159
get_intid_range(struct irq_data * d)160 static enum gic_intid_range get_intid_range(struct irq_data *d)
161 {
162 return __get_intid_range(d->hwirq);
163 }
164
gic_irq(struct irq_data * d)165 static inline unsigned int gic_irq(struct irq_data *d)
166 {
167 return d->hwirq;
168 }
169
gic_irq_in_rdist(struct irq_data * d)170 static inline bool gic_irq_in_rdist(struct irq_data *d)
171 {
172 switch (get_intid_range(d)) {
173 case SGI_RANGE:
174 case PPI_RANGE:
175 case EPPI_RANGE:
176 return true;
177 default:
178 return false;
179 }
180 }
181
gic_dist_base(struct irq_data * d)182 static inline void __iomem *gic_dist_base(struct irq_data *d)
183 {
184 switch (get_intid_range(d)) {
185 case SGI_RANGE:
186 case PPI_RANGE:
187 case EPPI_RANGE:
188 /* SGI+PPI -> SGI_base for this CPU */
189 return gic_data_rdist_sgi_base();
190
191 case SPI_RANGE:
192 case ESPI_RANGE:
193 /* SPI -> dist_base */
194 return gic_data.dist_base;
195
196 default:
197 return NULL;
198 }
199 }
200
gic_do_wait_for_rwp(void __iomem * base,u32 bit)201 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
202 {
203 u32 count = 1000000; /* 1s! */
204
205 while (readl_relaxed(base + GICD_CTLR) & bit) {
206 count--;
207 if (!count) {
208 pr_err_ratelimited("RWP timeout, gone fishing\n");
209 return;
210 }
211 cpu_relax();
212 udelay(1);
213 }
214 }
215
216 /* Wait for completion of a distributor change */
gic_dist_wait_for_rwp(void)217 static void gic_dist_wait_for_rwp(void)
218 {
219 gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
220 }
221
222 /* Wait for completion of a redistributor change */
gic_redist_wait_for_rwp(void)223 static void gic_redist_wait_for_rwp(void)
224 {
225 gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
226 }
227
228 #ifdef CONFIG_ARM64
229
gic_read_iar(void)230 static u64 __maybe_unused gic_read_iar(void)
231 {
232 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
233 return gic_read_iar_cavium_thunderx();
234 else
235 return gic_read_iar_common();
236 }
237 #endif
238
gic_enable_redist(bool enable)239 static void gic_enable_redist(bool enable)
240 {
241 void __iomem *rbase;
242 u32 count = 1000000; /* 1s! */
243 u32 val;
244
245 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
246 return;
247
248 rbase = gic_data_rdist_rd_base();
249
250 val = readl_relaxed(rbase + GICR_WAKER);
251 if (enable)
252 /* Wake up this CPU redistributor */
253 val &= ~GICR_WAKER_ProcessorSleep;
254 else
255 val |= GICR_WAKER_ProcessorSleep;
256 writel_relaxed(val, rbase + GICR_WAKER);
257
258 if (!enable) { /* Check that GICR_WAKER is writeable */
259 val = readl_relaxed(rbase + GICR_WAKER);
260 if (!(val & GICR_WAKER_ProcessorSleep))
261 return; /* No PM support in this redistributor */
262 }
263
264 while (--count) {
265 val = readl_relaxed(rbase + GICR_WAKER);
266 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
267 break;
268 cpu_relax();
269 udelay(1);
270 }
271 if (!count)
272 pr_err_ratelimited("redistributor failed to %s...\n",
273 enable ? "wakeup" : "sleep");
274 }
275
276 /*
277 * Routines to disable, enable, EOI and route interrupts
278 */
convert_offset_index(struct irq_data * d,u32 offset,u32 * index)279 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
280 {
281 switch (get_intid_range(d)) {
282 case SGI_RANGE:
283 case PPI_RANGE:
284 case SPI_RANGE:
285 *index = d->hwirq;
286 return offset;
287 case EPPI_RANGE:
288 /*
289 * Contrary to the ESPI range, the EPPI range is contiguous
290 * to the PPI range in the registers, so let's adjust the
291 * displacement accordingly. Consistency is overrated.
292 */
293 *index = d->hwirq - EPPI_BASE_INTID + 32;
294 return offset;
295 case ESPI_RANGE:
296 *index = d->hwirq - ESPI_BASE_INTID;
297 switch (offset) {
298 case GICD_ISENABLER:
299 return GICD_ISENABLERnE;
300 case GICD_ICENABLER:
301 return GICD_ICENABLERnE;
302 case GICD_ISPENDR:
303 return GICD_ISPENDRnE;
304 case GICD_ICPENDR:
305 return GICD_ICPENDRnE;
306 case GICD_ISACTIVER:
307 return GICD_ISACTIVERnE;
308 case GICD_ICACTIVER:
309 return GICD_ICACTIVERnE;
310 case GICD_IPRIORITYR:
311 return GICD_IPRIORITYRnE;
312 case GICD_ICFGR:
313 return GICD_ICFGRnE;
314 case GICD_IROUTER:
315 return GICD_IROUTERnE;
316 default:
317 break;
318 }
319 break;
320 default:
321 break;
322 }
323
324 WARN_ON(1);
325 *index = d->hwirq;
326 return offset;
327 }
328
gic_peek_irq(struct irq_data * d,u32 offset)329 static int gic_peek_irq(struct irq_data *d, u32 offset)
330 {
331 void __iomem *base;
332 u32 index, mask;
333
334 offset = convert_offset_index(d, offset, &index);
335 mask = 1 << (index % 32);
336
337 if (gic_irq_in_rdist(d))
338 base = gic_data_rdist_sgi_base();
339 else
340 base = gic_data.dist_base;
341
342 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
343 }
344
gic_poke_irq(struct irq_data * d,u32 offset)345 static void gic_poke_irq(struct irq_data *d, u32 offset)
346 {
347 void (*rwp_wait)(void);
348 void __iomem *base;
349 u32 index, mask;
350
351 offset = convert_offset_index(d, offset, &index);
352 mask = 1 << (index % 32);
353
354 if (gic_irq_in_rdist(d)) {
355 base = gic_data_rdist_sgi_base();
356 rwp_wait = gic_redist_wait_for_rwp;
357 } else {
358 base = gic_data.dist_base;
359 rwp_wait = gic_dist_wait_for_rwp;
360 }
361
362 writel_relaxed(mask, base + offset + (index / 32) * 4);
363 rwp_wait();
364 }
365
gic_mask_irq(struct irq_data * d)366 static void gic_mask_irq(struct irq_data *d)
367 {
368 gic_poke_irq(d, GICD_ICENABLER);
369 }
370
gic_eoimode1_mask_irq(struct irq_data * d)371 static void gic_eoimode1_mask_irq(struct irq_data *d)
372 {
373 gic_mask_irq(d);
374 /*
375 * When masking a forwarded interrupt, make sure it is
376 * deactivated as well.
377 *
378 * This ensures that an interrupt that is getting
379 * disabled/masked will not get "stuck", because there is
380 * noone to deactivate it (guest is being terminated).
381 */
382 if (irqd_is_forwarded_to_vcpu(d))
383 gic_poke_irq(d, GICD_ICACTIVER);
384 }
385
gic_unmask_irq(struct irq_data * d)386 static void gic_unmask_irq(struct irq_data *d)
387 {
388 gic_poke_irq(d, GICD_ISENABLER);
389 }
390
gic_supports_nmi(void)391 static inline bool gic_supports_nmi(void)
392 {
393 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
394 static_branch_likely(&supports_pseudo_nmis);
395 }
396
gic_irq_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool val)397 static int gic_irq_set_irqchip_state(struct irq_data *d,
398 enum irqchip_irq_state which, bool val)
399 {
400 u32 reg;
401
402 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */
403 return -EINVAL;
404
405 switch (which) {
406 case IRQCHIP_STATE_PENDING:
407 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
408 break;
409
410 case IRQCHIP_STATE_ACTIVE:
411 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
412 break;
413
414 case IRQCHIP_STATE_MASKED:
415 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
416 break;
417
418 default:
419 return -EINVAL;
420 }
421
422 gic_poke_irq(d, reg);
423 return 0;
424 }
425
gic_irq_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * val)426 static int gic_irq_get_irqchip_state(struct irq_data *d,
427 enum irqchip_irq_state which, bool *val)
428 {
429 if (d->hwirq >= 8192) /* PPI/SPI only */
430 return -EINVAL;
431
432 switch (which) {
433 case IRQCHIP_STATE_PENDING:
434 *val = gic_peek_irq(d, GICD_ISPENDR);
435 break;
436
437 case IRQCHIP_STATE_ACTIVE:
438 *val = gic_peek_irq(d, GICD_ISACTIVER);
439 break;
440
441 case IRQCHIP_STATE_MASKED:
442 *val = !gic_peek_irq(d, GICD_ISENABLER);
443 break;
444
445 default:
446 return -EINVAL;
447 }
448
449 return 0;
450 }
451
gic_irq_set_prio(struct irq_data * d,u8 prio)452 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
453 {
454 void __iomem *base = gic_dist_base(d);
455 u32 offset, index;
456
457 offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
458
459 writeb_relaxed(prio, base + offset + index);
460 }
461
gic_get_ppi_index(struct irq_data * d)462 static u32 gic_get_ppi_index(struct irq_data *d)
463 {
464 switch (get_intid_range(d)) {
465 case PPI_RANGE:
466 return d->hwirq - 16;
467 case EPPI_RANGE:
468 return d->hwirq - EPPI_BASE_INTID + 16;
469 default:
470 unreachable();
471 }
472 }
473
gic_irq_nmi_setup(struct irq_data * d)474 static int gic_irq_nmi_setup(struct irq_data *d)
475 {
476 struct irq_desc *desc = irq_to_desc(d->irq);
477
478 if (!gic_supports_nmi())
479 return -EINVAL;
480
481 if (gic_peek_irq(d, GICD_ISENABLER)) {
482 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
483 return -EINVAL;
484 }
485
486 /*
487 * A secondary irq_chip should be in charge of LPI request,
488 * it should not be possible to get there
489 */
490 if (WARN_ON(gic_irq(d) >= 8192))
491 return -EINVAL;
492
493 /* desc lock should already be held */
494 if (gic_irq_in_rdist(d)) {
495 u32 idx = gic_get_ppi_index(d);
496
497 /* Setting up PPI as NMI, only switch handler for first NMI */
498 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
499 refcount_set(&ppi_nmi_refs[idx], 1);
500 desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
501 }
502 } else {
503 desc->handle_irq = handle_fasteoi_nmi;
504 }
505
506 gic_irq_set_prio(d, GICD_INT_NMI_PRI);
507
508 return 0;
509 }
510
gic_irq_nmi_teardown(struct irq_data * d)511 static void gic_irq_nmi_teardown(struct irq_data *d)
512 {
513 struct irq_desc *desc = irq_to_desc(d->irq);
514
515 if (WARN_ON(!gic_supports_nmi()))
516 return;
517
518 if (gic_peek_irq(d, GICD_ISENABLER)) {
519 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
520 return;
521 }
522
523 /*
524 * A secondary irq_chip should be in charge of LPI request,
525 * it should not be possible to get there
526 */
527 if (WARN_ON(gic_irq(d) >= 8192))
528 return;
529
530 /* desc lock should already be held */
531 if (gic_irq_in_rdist(d)) {
532 u32 idx = gic_get_ppi_index(d);
533
534 /* Tearing down NMI, only switch handler for last NMI */
535 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
536 desc->handle_irq = handle_percpu_devid_irq;
537 } else {
538 desc->handle_irq = handle_fasteoi_irq;
539 }
540
541 gic_irq_set_prio(d, GICD_INT_DEF_PRI);
542 }
543
gic_eoi_irq(struct irq_data * d)544 static void gic_eoi_irq(struct irq_data *d)
545 {
546 gic_write_eoir(gic_irq(d));
547 }
548
gic_eoimode1_eoi_irq(struct irq_data * d)549 static void gic_eoimode1_eoi_irq(struct irq_data *d)
550 {
551 /*
552 * No need to deactivate an LPI, or an interrupt that
553 * is is getting forwarded to a vcpu.
554 */
555 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
556 return;
557 gic_write_dir(gic_irq(d));
558 }
559
gic_set_type(struct irq_data * d,unsigned int type)560 static int gic_set_type(struct irq_data *d, unsigned int type)
561 {
562 enum gic_intid_range range;
563 unsigned int irq = gic_irq(d);
564 void (*rwp_wait)(void);
565 void __iomem *base;
566 u32 offset, index;
567 int ret;
568
569 range = get_intid_range(d);
570
571 /* Interrupt configuration for SGIs can't be changed */
572 if (range == SGI_RANGE)
573 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
574
575 /* SPIs have restrictions on the supported types */
576 if ((range == SPI_RANGE || range == ESPI_RANGE) &&
577 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
578 return -EINVAL;
579
580 if (gic_irq_in_rdist(d)) {
581 base = gic_data_rdist_sgi_base();
582 rwp_wait = gic_redist_wait_for_rwp;
583 } else {
584 base = gic_data.dist_base;
585 rwp_wait = gic_dist_wait_for_rwp;
586 }
587
588 offset = convert_offset_index(d, GICD_ICFGR, &index);
589
590 ret = gic_configure_irq(index, type, base + offset, rwp_wait);
591 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
592 /* Misconfigured PPIs are usually not fatal */
593 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
594 ret = 0;
595 }
596
597 return ret;
598 }
599
gic_irq_set_vcpu_affinity(struct irq_data * d,void * vcpu)600 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
601 {
602 if (get_intid_range(d) == SGI_RANGE)
603 return -EINVAL;
604
605 if (vcpu)
606 irqd_set_forwarded_to_vcpu(d);
607 else
608 irqd_clr_forwarded_to_vcpu(d);
609 return 0;
610 }
611
gic_mpidr_to_affinity(unsigned long mpidr)612 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
613 {
614 u64 aff;
615
616 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
617 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
618 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
619 MPIDR_AFFINITY_LEVEL(mpidr, 0));
620
621 return aff;
622 }
623
gic_deactivate_unhandled(u32 irqnr)624 static void gic_deactivate_unhandled(u32 irqnr)
625 {
626 if (static_branch_likely(&supports_deactivate_key)) {
627 if (irqnr < 8192)
628 gic_write_dir(irqnr);
629 } else {
630 gic_write_eoir(irqnr);
631 }
632 }
633
gic_handle_nmi(u32 irqnr,struct pt_regs * regs)634 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
635 {
636 bool irqs_enabled = interrupts_enabled(regs);
637 int err;
638
639 if (irqs_enabled)
640 nmi_enter();
641
642 if (static_branch_likely(&supports_deactivate_key))
643 gic_write_eoir(irqnr);
644 /*
645 * Leave the PSR.I bit set to prevent other NMIs to be
646 * received while handling this one.
647 * PSR.I will be restored when we ERET to the
648 * interrupted context.
649 */
650 err = handle_domain_nmi(gic_data.domain, irqnr, regs);
651 if (err)
652 gic_deactivate_unhandled(irqnr);
653
654 if (irqs_enabled)
655 nmi_exit();
656 }
657
do_read_iar(struct pt_regs * regs)658 static u32 do_read_iar(struct pt_regs *regs)
659 {
660 u32 iar;
661
662 if (gic_supports_nmi() && unlikely(!interrupts_enabled(regs))) {
663 u64 pmr;
664
665 /*
666 * We were in a context with IRQs disabled. However, the
667 * entry code has set PMR to a value that allows any
668 * interrupt to be acknowledged, and not just NMIs. This can
669 * lead to surprising effects if the NMI has been retired in
670 * the meantime, and that there is an IRQ pending. The IRQ
671 * would then be taken in NMI context, something that nobody
672 * wants to debug twice.
673 *
674 * Until we sort this, drop PMR again to a level that will
675 * actually only allow NMIs before reading IAR, and then
676 * restore it to what it was.
677 */
678 pmr = gic_read_pmr();
679 gic_pmr_mask_irqs();
680 isb();
681
682 iar = gic_read_iar();
683
684 gic_write_pmr(pmr);
685 } else {
686 iar = gic_read_iar();
687 }
688
689 return iar;
690 }
691
gic_handle_irq(struct pt_regs * regs)692 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
693 {
694 u32 irqnr;
695
696 irqnr = do_read_iar(regs);
697
698 /* Check for special IDs first */
699 if ((irqnr >= 1020 && irqnr <= 1023))
700 return;
701
702 if (gic_supports_nmi() &&
703 unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) {
704 gic_handle_nmi(irqnr, regs);
705 return;
706 }
707
708 if (gic_prio_masking_enabled()) {
709 gic_pmr_mask_irqs();
710 gic_arch_enable_irqs();
711 }
712
713 if (static_branch_likely(&supports_deactivate_key))
714 gic_write_eoir(irqnr);
715 else
716 isb();
717
718 if (handle_domain_irq(gic_data.domain, irqnr, regs)) {
719 WARN_ONCE(true, "Unexpected interrupt received!\n");
720 log_abnormal_wakeup_reason("unexpected HW IRQ %u", irqnr);
721 gic_deactivate_unhandled(irqnr);
722 }
723 }
724
gic_get_pribits(void)725 static u32 gic_get_pribits(void)
726 {
727 u32 pribits;
728
729 pribits = gic_read_ctlr();
730 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
731 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
732 pribits++;
733
734 return pribits;
735 }
736
gic_has_group0(void)737 static bool gic_has_group0(void)
738 {
739 u32 val;
740 u32 old_pmr;
741
742 old_pmr = gic_read_pmr();
743
744 /*
745 * Let's find out if Group0 is under control of EL3 or not by
746 * setting the highest possible, non-zero priority in PMR.
747 *
748 * If SCR_EL3.FIQ is set, the priority gets shifted down in
749 * order for the CPU interface to set bit 7, and keep the
750 * actual priority in the non-secure range. In the process, it
751 * looses the least significant bit and the actual priority
752 * becomes 0x80. Reading it back returns 0, indicating that
753 * we're don't have access to Group0.
754 */
755 gic_write_pmr(BIT(8 - gic_get_pribits()));
756 val = gic_read_pmr();
757
758 gic_write_pmr(old_pmr);
759
760 return val != 0;
761 }
762
gic_dist_init(void)763 static void __init gic_dist_init(void)
764 {
765 unsigned int i;
766 u64 affinity;
767 void __iomem *base = gic_data.dist_base;
768 u32 val;
769
770 /* Disable the distributor */
771 writel_relaxed(0, base + GICD_CTLR);
772 gic_dist_wait_for_rwp();
773
774 /*
775 * Configure SPIs as non-secure Group-1. This will only matter
776 * if the GIC only has a single security state. This will not
777 * do the right thing if the kernel is running in secure mode,
778 * but that's not the intended use case anyway.
779 */
780 for (i = 32; i < GIC_LINE_NR; i += 32)
781 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
782
783 /* Extended SPI range, not handled by the GICv2/GICv3 common code */
784 for (i = 0; i < GIC_ESPI_NR; i += 32) {
785 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
786 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
787 }
788
789 for (i = 0; i < GIC_ESPI_NR; i += 32)
790 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
791
792 for (i = 0; i < GIC_ESPI_NR; i += 16)
793 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
794
795 for (i = 0; i < GIC_ESPI_NR; i += 4)
796 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
797
798 /* Now do the common stuff, and wait for the distributor to drain */
799 gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
800
801 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
802 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
803 pr_info("Enabling SGIs without active state\n");
804 val |= GICD_CTLR_nASSGIreq;
805 }
806
807 /* Enable distributor with ARE, Group1 */
808 writel_relaxed(val, base + GICD_CTLR);
809
810 /*
811 * Set all global interrupts to the boot CPU only. ARE must be
812 * enabled.
813 */
814 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
815 for (i = 32; i < GIC_LINE_NR; i++)
816 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
817
818 for (i = 0; i < GIC_ESPI_NR; i++)
819 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
820 }
821
gic_iterate_rdists(int (* fn)(struct redist_region *,void __iomem *))822 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
823 {
824 int ret = -ENODEV;
825 int i;
826
827 for (i = 0; i < gic_data.nr_redist_regions; i++) {
828 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
829 u64 typer;
830 u32 reg;
831
832 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
833 if (reg != GIC_PIDR2_ARCH_GICv3 &&
834 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
835 pr_warn("No redistributor present @%p\n", ptr);
836 break;
837 }
838
839 do {
840 typer = gic_read_typer(ptr + GICR_TYPER);
841 ret = fn(gic_data.redist_regions + i, ptr);
842 if (!ret)
843 return 0;
844
845 if (gic_data.redist_regions[i].single_redist)
846 break;
847
848 if (gic_data.redist_stride) {
849 ptr += gic_data.redist_stride;
850 } else {
851 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
852 if (typer & GICR_TYPER_VLPIS)
853 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
854 }
855 } while (!(typer & GICR_TYPER_LAST));
856 }
857
858 return ret ? -ENODEV : 0;
859 }
860
__gic_populate_rdist(struct redist_region * region,void __iomem * ptr)861 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
862 {
863 unsigned long mpidr = cpu_logical_map(smp_processor_id());
864 u64 typer;
865 u32 aff;
866
867 /*
868 * Convert affinity to a 32bit value that can be matched to
869 * GICR_TYPER bits [63:32].
870 */
871 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
872 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
873 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
874 MPIDR_AFFINITY_LEVEL(mpidr, 0));
875
876 typer = gic_read_typer(ptr + GICR_TYPER);
877 if ((typer >> 32) == aff) {
878 u64 offset = ptr - region->redist_base;
879 raw_spin_lock_init(&gic_data_rdist()->rd_lock);
880 gic_data_rdist_rd_base() = ptr;
881 gic_data_rdist()->phys_base = region->phys_base + offset;
882
883 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
884 smp_processor_id(), mpidr,
885 (int)(region - gic_data.redist_regions),
886 &gic_data_rdist()->phys_base);
887 return 0;
888 }
889
890 /* Try next one */
891 return 1;
892 }
893
gic_populate_rdist(void)894 static int gic_populate_rdist(void)
895 {
896 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
897 return 0;
898
899 /* We couldn't even deal with ourselves... */
900 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
901 smp_processor_id(),
902 (unsigned long)cpu_logical_map(smp_processor_id()));
903 return -ENODEV;
904 }
905
__gic_update_rdist_properties(struct redist_region * region,void __iomem * ptr)906 static int __gic_update_rdist_properties(struct redist_region *region,
907 void __iomem *ptr)
908 {
909 u64 typer = gic_read_typer(ptr + GICR_TYPER);
910
911 /* Boot-time cleanip */
912 if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) {
913 u64 val;
914
915 /* Deactivate any present vPE */
916 val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
917 if (val & GICR_VPENDBASER_Valid)
918 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
919 ptr + SZ_128K + GICR_VPENDBASER);
920
921 /* Mark the VPE table as invalid */
922 val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
923 val &= ~GICR_VPROPBASER_4_1_VALID;
924 gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
925 }
926
927 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
928
929 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */
930 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
931 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
932 gic_data.rdists.has_rvpeid);
933 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
934
935 /* Detect non-sensical configurations */
936 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
937 gic_data.rdists.has_direct_lpi = false;
938 gic_data.rdists.has_vlpis = false;
939 gic_data.rdists.has_rvpeid = false;
940 }
941
942 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
943
944 return 1;
945 }
946
gic_update_rdist_properties(void)947 static void gic_update_rdist_properties(void)
948 {
949 gic_data.ppi_nr = UINT_MAX;
950 gic_iterate_rdists(__gic_update_rdist_properties);
951 if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
952 gic_data.ppi_nr = 0;
953 pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
954 if (gic_data.rdists.has_vlpis)
955 pr_info("GICv4 features: %s%s%s\n",
956 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
957 gic_data.rdists.has_rvpeid ? "RVPEID " : "",
958 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
959 }
960
961 /* Check whether it's single security state view */
gic_dist_security_disabled(void)962 static inline bool gic_dist_security_disabled(void)
963 {
964 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
965 }
966
gic_cpu_sys_reg_init(void)967 static void gic_cpu_sys_reg_init(void)
968 {
969 int i, cpu = smp_processor_id();
970 u64 mpidr = cpu_logical_map(cpu);
971 u64 need_rss = MPIDR_RS(mpidr);
972 bool group0;
973 u32 pribits;
974
975 /*
976 * Need to check that the SRE bit has actually been set. If
977 * not, it means that SRE is disabled at EL2. We're going to
978 * die painfully, and there is nothing we can do about it.
979 *
980 * Kindly inform the luser.
981 */
982 if (!gic_enable_sre())
983 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
984
985 pribits = gic_get_pribits();
986
987 group0 = gic_has_group0();
988
989 /* Set priority mask register */
990 if (!gic_prio_masking_enabled()) {
991 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
992 } else if (gic_supports_nmi()) {
993 /*
994 * Mismatch configuration with boot CPU, the system is likely
995 * to die as interrupt masking will not work properly on all
996 * CPUs
997 *
998 * The boot CPU calls this function before enabling NMI support,
999 * and as a result we'll never see this warning in the boot path
1000 * for that CPU.
1001 */
1002 if (static_branch_unlikely(&gic_nonsecure_priorities))
1003 WARN_ON(!group0 || gic_dist_security_disabled());
1004 else
1005 WARN_ON(group0 && !gic_dist_security_disabled());
1006 }
1007
1008 /*
1009 * Some firmwares hand over to the kernel with the BPR changed from
1010 * its reset value (and with a value large enough to prevent
1011 * any pre-emptive interrupts from working at all). Writing a zero
1012 * to BPR restores is reset value.
1013 */
1014 gic_write_bpr1(0);
1015
1016 if (static_branch_likely(&supports_deactivate_key)) {
1017 /* EOI drops priority only (mode 1) */
1018 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
1019 } else {
1020 /* EOI deactivates interrupt too (mode 0) */
1021 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
1022 }
1023
1024 /* Always whack Group0 before Group1 */
1025 if (group0) {
1026 switch(pribits) {
1027 case 8:
1028 case 7:
1029 write_gicreg(0, ICC_AP0R3_EL1);
1030 write_gicreg(0, ICC_AP0R2_EL1);
1031 fallthrough;
1032 case 6:
1033 write_gicreg(0, ICC_AP0R1_EL1);
1034 fallthrough;
1035 case 5:
1036 case 4:
1037 write_gicreg(0, ICC_AP0R0_EL1);
1038 }
1039
1040 isb();
1041 }
1042
1043 switch(pribits) {
1044 case 8:
1045 case 7:
1046 write_gicreg(0, ICC_AP1R3_EL1);
1047 write_gicreg(0, ICC_AP1R2_EL1);
1048 fallthrough;
1049 case 6:
1050 write_gicreg(0, ICC_AP1R1_EL1);
1051 fallthrough;
1052 case 5:
1053 case 4:
1054 write_gicreg(0, ICC_AP1R0_EL1);
1055 }
1056
1057 isb();
1058
1059 /* ... and let's hit the road... */
1060 gic_write_grpen1(1);
1061
1062 /* Keep the RSS capability status in per_cpu variable */
1063 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
1064
1065 /* Check all the CPUs have capable of sending SGIs to other CPUs */
1066 for_each_online_cpu(i) {
1067 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
1068
1069 need_rss |= MPIDR_RS(cpu_logical_map(i));
1070 if (need_rss && (!have_rss))
1071 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1072 cpu, (unsigned long)mpidr,
1073 i, (unsigned long)cpu_logical_map(i));
1074 }
1075
1076 /**
1077 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1078 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1079 * UNPREDICTABLE choice of :
1080 * - The write is ignored.
1081 * - The RS field is treated as 0.
1082 */
1083 if (need_rss && (!gic_data.has_rss))
1084 pr_crit_once("RSS is required but GICD doesn't support it\n");
1085 }
1086
1087 static bool gicv3_nolpi;
1088
gicv3_nolpi_cfg(char * buf)1089 static int __init gicv3_nolpi_cfg(char *buf)
1090 {
1091 return strtobool(buf, &gicv3_nolpi);
1092 }
1093 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1094
gic_dist_supports_lpis(void)1095 static int gic_dist_supports_lpis(void)
1096 {
1097 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1098 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1099 !gicv3_nolpi);
1100 }
1101
gic_cpu_init(void)1102 static void gic_cpu_init(void)
1103 {
1104 void __iomem *rbase;
1105 int i;
1106
1107 /* Register ourselves with the rest of the world */
1108 if (gic_populate_rdist())
1109 return;
1110
1111 gic_enable_redist(true);
1112
1113 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1114 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1115 "Distributor has extended ranges, but CPU%d doesn't\n",
1116 smp_processor_id());
1117
1118 rbase = gic_data_rdist_sgi_base();
1119
1120 /* Configure SGIs/PPIs as non-secure Group-1 */
1121 for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1122 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1123
1124 gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
1125
1126 /* initialise system registers */
1127 gic_cpu_sys_reg_init();
1128 }
1129
1130 #ifdef CONFIG_SMP
1131
1132 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1133 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
1134
gic_starting_cpu(unsigned int cpu)1135 static int gic_starting_cpu(unsigned int cpu)
1136 {
1137 gic_cpu_init();
1138
1139 if (gic_dist_supports_lpis())
1140 its_cpu_init();
1141
1142 return 0;
1143 }
1144
gic_compute_target_list(int * base_cpu,const struct cpumask * mask,unsigned long cluster_id)1145 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
1146 unsigned long cluster_id)
1147 {
1148 int next_cpu, cpu = *base_cpu;
1149 unsigned long mpidr = cpu_logical_map(cpu);
1150 u16 tlist = 0;
1151
1152 while (cpu < nr_cpu_ids) {
1153 tlist |= 1 << (mpidr & 0xf);
1154
1155 next_cpu = cpumask_next(cpu, mask);
1156 if (next_cpu >= nr_cpu_ids)
1157 goto out;
1158 cpu = next_cpu;
1159
1160 mpidr = cpu_logical_map(cpu);
1161
1162 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
1163 cpu--;
1164 goto out;
1165 }
1166 }
1167 out:
1168 *base_cpu = cpu;
1169 return tlist;
1170 }
1171
1172 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1173 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1174 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1175
gic_send_sgi(u64 cluster_id,u16 tlist,unsigned int irq)1176 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1177 {
1178 u64 val;
1179
1180 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
1181 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
1182 irq << ICC_SGI1R_SGI_ID_SHIFT |
1183 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
1184 MPIDR_TO_SGI_RS(cluster_id) |
1185 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
1186
1187 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1188 gic_write_sgi1r(val);
1189 }
1190
gic_ipi_send_mask(struct irq_data * d,const struct cpumask * mask)1191 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
1192 {
1193 int cpu;
1194
1195 if (WARN_ON(d->hwirq >= 16))
1196 return;
1197
1198 /*
1199 * Ensure that stores to Normal memory are visible to the
1200 * other CPUs before issuing the IPI.
1201 */
1202 wmb();
1203
1204 for_each_cpu(cpu, mask) {
1205 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
1206 u16 tlist;
1207
1208 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1209 gic_send_sgi(cluster_id, tlist, d->hwirq);
1210 }
1211
1212 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1213 isb();
1214 }
1215
gic_smp_init(void)1216 static void __init gic_smp_init(void)
1217 {
1218 struct irq_fwspec sgi_fwspec = {
1219 .fwnode = gic_data.fwnode,
1220 .param_count = 1,
1221 };
1222 int base_sgi;
1223
1224 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1225 "irqchip/arm/gicv3:starting",
1226 gic_starting_cpu, NULL);
1227
1228 /* Register all 8 non-secure SGIs */
1229 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8,
1230 NUMA_NO_NODE, &sgi_fwspec,
1231 false, NULL);
1232 if (WARN_ON(base_sgi <= 0))
1233 return;
1234
1235 set_smp_ipi_range(base_sgi, 8);
1236 }
1237
gic_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)1238 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1239 bool force)
1240 {
1241 unsigned int cpu;
1242 u32 offset, index;
1243 void __iomem *reg;
1244 int enabled;
1245 u64 val;
1246
1247 if (force)
1248 cpu = cpumask_first(mask_val);
1249 else
1250 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1251
1252 if (cpu >= nr_cpu_ids)
1253 return -EINVAL;
1254
1255 if (gic_irq_in_rdist(d))
1256 return -EINVAL;
1257
1258 /* If interrupt was enabled, disable it first */
1259 enabled = gic_peek_irq(d, GICD_ISENABLER);
1260 if (enabled)
1261 gic_mask_irq(d);
1262
1263 offset = convert_offset_index(d, GICD_IROUTER, &index);
1264 reg = gic_dist_base(d) + offset + (index * 8);
1265 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1266
1267 trace_android_rvh_gic_v3_set_affinity(d, mask_val, &val, force, gic_dist_base(d));
1268 gic_write_irouter(val, reg);
1269
1270 /*
1271 * If the interrupt was enabled, enabled it again. Otherwise,
1272 * just wait for the distributor to have digested our changes.
1273 */
1274 if (enabled)
1275 gic_unmask_irq(d);
1276 else
1277 gic_dist_wait_for_rwp();
1278
1279 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1280
1281 return IRQ_SET_MASK_OK_DONE;
1282 }
1283 #else
1284 #define gic_set_affinity NULL
1285 #define gic_ipi_send_mask NULL
1286 #define gic_smp_init() do { } while(0)
1287 #endif
1288
gic_retrigger(struct irq_data * data)1289 static int gic_retrigger(struct irq_data *data)
1290 {
1291 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
1292 }
1293
1294 #ifdef CONFIG_CPU_PM
gic_cpu_pm_notifier(struct notifier_block * self,unsigned long cmd,void * v)1295 static int gic_cpu_pm_notifier(struct notifier_block *self,
1296 unsigned long cmd, void *v)
1297 {
1298 if (cmd == CPU_PM_EXIT) {
1299 if (gic_dist_security_disabled())
1300 gic_enable_redist(true);
1301 gic_cpu_sys_reg_init();
1302 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1303 gic_write_grpen1(0);
1304 gic_enable_redist(false);
1305 }
1306 return NOTIFY_OK;
1307 }
1308
1309 static struct notifier_block gic_cpu_pm_notifier_block = {
1310 .notifier_call = gic_cpu_pm_notifier,
1311 };
1312
gic_cpu_pm_init(void)1313 static void gic_cpu_pm_init(void)
1314 {
1315 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1316 }
1317
1318 #else
gic_cpu_pm_init(void)1319 static inline void gic_cpu_pm_init(void) { }
1320 #endif /* CONFIG_CPU_PM */
1321
1322 #ifdef CONFIG_PM
gic_resume(void)1323 void gic_resume(void)
1324 {
1325 trace_android_vh_gic_resume(&gic_data);
1326 }
1327 EXPORT_SYMBOL_GPL(gic_resume);
1328
1329 static struct syscore_ops gic_syscore_ops = {
1330 .resume = gic_resume,
1331 };
1332
gic_syscore_init(void)1333 static void gic_syscore_init(void)
1334 {
1335 register_syscore_ops(&gic_syscore_ops);
1336 }
1337
1338 #else
gic_syscore_init(void)1339 static inline void gic_syscore_init(void) { }
gic_resume(void)1340 void gic_resume(void) { }
1341 #endif
1342
1343
1344 static struct irq_chip gic_chip = {
1345 .name = "GICv3",
1346 .irq_mask = gic_mask_irq,
1347 .irq_unmask = gic_unmask_irq,
1348 .irq_eoi = gic_eoi_irq,
1349 .irq_set_type = gic_set_type,
1350 .irq_set_affinity = gic_set_affinity,
1351 .irq_retrigger = gic_retrigger,
1352 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1353 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1354 .irq_nmi_setup = gic_irq_nmi_setup,
1355 .irq_nmi_teardown = gic_irq_nmi_teardown,
1356 .ipi_send_mask = gic_ipi_send_mask,
1357 .flags = IRQCHIP_SET_TYPE_MASKED |
1358 IRQCHIP_SKIP_SET_WAKE |
1359 IRQCHIP_MASK_ON_SUSPEND,
1360 };
1361
1362 static struct irq_chip gic_eoimode1_chip = {
1363 .name = "GICv3",
1364 .irq_mask = gic_eoimode1_mask_irq,
1365 .irq_unmask = gic_unmask_irq,
1366 .irq_eoi = gic_eoimode1_eoi_irq,
1367 .irq_set_type = gic_set_type,
1368 .irq_set_affinity = gic_set_affinity,
1369 .irq_retrigger = gic_retrigger,
1370 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1371 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1372 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
1373 .irq_nmi_setup = gic_irq_nmi_setup,
1374 .irq_nmi_teardown = gic_irq_nmi_teardown,
1375 .ipi_send_mask = gic_ipi_send_mask,
1376 .flags = IRQCHIP_SET_TYPE_MASKED |
1377 IRQCHIP_SKIP_SET_WAKE |
1378 IRQCHIP_MASK_ON_SUSPEND,
1379 };
1380
gic_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)1381 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1382 irq_hw_number_t hw)
1383 {
1384 struct irq_chip *chip = &gic_chip;
1385 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1386
1387 if (static_branch_likely(&supports_deactivate_key))
1388 chip = &gic_eoimode1_chip;
1389
1390 switch (__get_intid_range(hw)) {
1391 case SGI_RANGE:
1392 irq_set_percpu_devid(irq);
1393 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1394 handle_percpu_devid_fasteoi_ipi,
1395 NULL, NULL);
1396 break;
1397
1398 case PPI_RANGE:
1399 case EPPI_RANGE:
1400 irq_set_percpu_devid(irq);
1401 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1402 handle_percpu_devid_irq, NULL, NULL);
1403 break;
1404
1405 case SPI_RANGE:
1406 case ESPI_RANGE:
1407 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1408 handle_fasteoi_irq, NULL, NULL);
1409 irq_set_probe(irq);
1410 irqd_set_single_target(irqd);
1411 break;
1412
1413 case LPI_RANGE:
1414 if (!gic_dist_supports_lpis())
1415 return -EPERM;
1416 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1417 handle_fasteoi_irq, NULL, NULL);
1418 break;
1419
1420 default:
1421 return -EPERM;
1422 }
1423
1424 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1425 irqd_set_handle_enforce_irqctx(irqd);
1426 return 0;
1427 }
1428
gic_irq_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1429 static int gic_irq_domain_translate(struct irq_domain *d,
1430 struct irq_fwspec *fwspec,
1431 unsigned long *hwirq,
1432 unsigned int *type)
1433 {
1434 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1435 *hwirq = fwspec->param[0];
1436 *type = IRQ_TYPE_EDGE_RISING;
1437 return 0;
1438 }
1439
1440 if (is_of_node(fwspec->fwnode)) {
1441 if (fwspec->param_count < 3)
1442 return -EINVAL;
1443
1444 switch (fwspec->param[0]) {
1445 case 0: /* SPI */
1446 *hwirq = fwspec->param[1] + 32;
1447 break;
1448 case 1: /* PPI */
1449 *hwirq = fwspec->param[1] + 16;
1450 break;
1451 case 2: /* ESPI */
1452 *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1453 break;
1454 case 3: /* EPPI */
1455 *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1456 break;
1457 case GIC_IRQ_TYPE_LPI: /* LPI */
1458 *hwirq = fwspec->param[1];
1459 break;
1460 case GIC_IRQ_TYPE_PARTITION:
1461 *hwirq = fwspec->param[1];
1462 if (fwspec->param[1] >= 16)
1463 *hwirq += EPPI_BASE_INTID - 16;
1464 else
1465 *hwirq += 16;
1466 break;
1467 default:
1468 return -EINVAL;
1469 }
1470
1471 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1472
1473 /*
1474 * Make it clear that broken DTs are... broken.
1475 * Partitionned PPIs are an unfortunate exception.
1476 */
1477 WARN_ON(*type == IRQ_TYPE_NONE &&
1478 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1479 return 0;
1480 }
1481
1482 if (is_fwnode_irqchip(fwspec->fwnode)) {
1483 if(fwspec->param_count != 2)
1484 return -EINVAL;
1485
1486 if (fwspec->param[0] < 16) {
1487 pr_err(FW_BUG "Illegal GSI%d translation request\n",
1488 fwspec->param[0]);
1489 return -EINVAL;
1490 }
1491
1492 *hwirq = fwspec->param[0];
1493 *type = fwspec->param[1];
1494
1495 WARN_ON(*type == IRQ_TYPE_NONE);
1496 return 0;
1497 }
1498
1499 return -EINVAL;
1500 }
1501
gic_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)1502 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1503 unsigned int nr_irqs, void *arg)
1504 {
1505 int i, ret;
1506 irq_hw_number_t hwirq;
1507 unsigned int type = IRQ_TYPE_NONE;
1508 struct irq_fwspec *fwspec = arg;
1509
1510 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1511 if (ret)
1512 return ret;
1513
1514 for (i = 0; i < nr_irqs; i++) {
1515 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1516 if (ret)
1517 return ret;
1518 }
1519
1520 return 0;
1521 }
1522
gic_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)1523 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1524 unsigned int nr_irqs)
1525 {
1526 int i;
1527
1528 for (i = 0; i < nr_irqs; i++) {
1529 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1530 irq_set_handler(virq + i, NULL);
1531 irq_domain_reset_irq_data(d);
1532 }
1533 }
1534
gic_irq_domain_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)1535 static int gic_irq_domain_select(struct irq_domain *d,
1536 struct irq_fwspec *fwspec,
1537 enum irq_domain_bus_token bus_token)
1538 {
1539 /* Not for us */
1540 if (fwspec->fwnode != d->fwnode)
1541 return 0;
1542
1543 /* If this is not DT, then we have a single domain */
1544 if (!is_of_node(fwspec->fwnode))
1545 return 1;
1546
1547 /*
1548 * If this is a PPI and we have a 4th (non-null) parameter,
1549 * then we need to match the partition domain.
1550 */
1551 if (fwspec->param_count >= 4 &&
1552 fwspec->param[0] == 1 && fwspec->param[3] != 0 &&
1553 gic_data.ppi_descs)
1554 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1555
1556 return d == gic_data.domain;
1557 }
1558
1559 static const struct irq_domain_ops gic_irq_domain_ops = {
1560 .translate = gic_irq_domain_translate,
1561 .alloc = gic_irq_domain_alloc,
1562 .free = gic_irq_domain_free,
1563 .select = gic_irq_domain_select,
1564 };
1565
partition_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1566 static int partition_domain_translate(struct irq_domain *d,
1567 struct irq_fwspec *fwspec,
1568 unsigned long *hwirq,
1569 unsigned int *type)
1570 {
1571 struct device_node *np;
1572 int ret;
1573
1574 if (!gic_data.ppi_descs)
1575 return -ENOMEM;
1576
1577 np = of_find_node_by_phandle(fwspec->param[3]);
1578 if (WARN_ON(!np))
1579 return -EINVAL;
1580
1581 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1582 of_node_to_fwnode(np));
1583 if (ret < 0)
1584 return ret;
1585
1586 *hwirq = ret;
1587 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1588
1589 return 0;
1590 }
1591
1592 static const struct irq_domain_ops partition_domain_ops = {
1593 .translate = partition_domain_translate,
1594 .select = gic_irq_domain_select,
1595 };
1596
gic_enable_quirk_msm8996(void * data)1597 static bool gic_enable_quirk_msm8996(void *data)
1598 {
1599 struct gic_chip_data *d = data;
1600
1601 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1602
1603 return true;
1604 }
1605
gic_enable_quirk_cavium_38539(void * data)1606 static bool gic_enable_quirk_cavium_38539(void *data)
1607 {
1608 struct gic_chip_data *d = data;
1609
1610 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1611
1612 return true;
1613 }
1614
gic_enable_quirk_hip06_07(void * data)1615 static bool gic_enable_quirk_hip06_07(void *data)
1616 {
1617 struct gic_chip_data *d = data;
1618
1619 /*
1620 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1621 * not being an actual ARM implementation). The saving grace is
1622 * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1623 * HIP07 doesn't even have a proper IIDR, and still pretends to
1624 * have ESPI. In both cases, put them right.
1625 */
1626 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1627 /* Zero both ESPI and the RES0 field next to it... */
1628 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1629 return true;
1630 }
1631
1632 return false;
1633 }
1634
1635 static const struct gic_quirk gic_quirks[] = {
1636 {
1637 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1638 .compatible = "qcom,msm8996-gic-v3",
1639 .init = gic_enable_quirk_msm8996,
1640 },
1641 {
1642 .desc = "GICv3: HIP06 erratum 161010803",
1643 .iidr = 0x0204043b,
1644 .mask = 0xffffffff,
1645 .init = gic_enable_quirk_hip06_07,
1646 },
1647 {
1648 .desc = "GICv3: HIP07 erratum 161010803",
1649 .iidr = 0x00000000,
1650 .mask = 0xffffffff,
1651 .init = gic_enable_quirk_hip06_07,
1652 },
1653 {
1654 /*
1655 * Reserved register accesses generate a Synchronous
1656 * External Abort. This erratum applies to:
1657 * - ThunderX: CN88xx
1658 * - OCTEON TX: CN83xx, CN81xx
1659 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1660 */
1661 .desc = "GICv3: Cavium erratum 38539",
1662 .iidr = 0xa000034c,
1663 .mask = 0xe8f00fff,
1664 .init = gic_enable_quirk_cavium_38539,
1665 },
1666 {
1667 }
1668 };
1669
gic_enable_nmi_support(void)1670 static void gic_enable_nmi_support(void)
1671 {
1672 int i;
1673
1674 if (!gic_prio_masking_enabled())
1675 return;
1676
1677 ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1678 if (!ppi_nmi_refs)
1679 return;
1680
1681 for (i = 0; i < gic_data.ppi_nr; i++)
1682 refcount_set(&ppi_nmi_refs[i], 0);
1683
1684 /*
1685 * Linux itself doesn't use 1:N distribution, so has no need to
1686 * set PMHE. The only reason to have it set is if EL3 requires it
1687 * (and we can't change it).
1688 */
1689 if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
1690 static_branch_enable(&gic_pmr_sync);
1691
1692 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
1693 static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
1694
1695 /*
1696 * How priority values are used by the GIC depends on two things:
1697 * the security state of the GIC (controlled by the GICD_CTRL.DS bit)
1698 * and if Group 0 interrupts can be delivered to Linux in the non-secure
1699 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
1700 * the ICC_PMR_EL1 register and the priority that software assigns to
1701 * interrupts:
1702 *
1703 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority
1704 * -----------------------------------------------------------
1705 * 1 | - | unchanged | unchanged
1706 * -----------------------------------------------------------
1707 * 0 | 1 | non-secure | non-secure
1708 * -----------------------------------------------------------
1709 * 0 | 0 | unchanged | non-secure
1710 *
1711 * where non-secure means that the value is right-shifted by one and the
1712 * MSB bit set, to make it fit in the non-secure priority range.
1713 *
1714 * In the first two cases, where ICC_PMR_EL1 and the interrupt priority
1715 * are both either modified or unchanged, we can use the same set of
1716 * priorities.
1717 *
1718 * In the last case, where only the interrupt priorities are modified to
1719 * be in the non-secure range, we use a different PMR value to mask IRQs
1720 * and the rest of the values that we use remain unchanged.
1721 */
1722 if (gic_has_group0() && !gic_dist_security_disabled())
1723 static_branch_enable(&gic_nonsecure_priorities);
1724
1725 static_branch_enable(&supports_pseudo_nmis);
1726
1727 if (static_branch_likely(&supports_deactivate_key))
1728 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1729 else
1730 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1731 }
1732
gic_init_bases(void __iomem * dist_base,struct redist_region * rdist_regs,u32 nr_redist_regions,u64 redist_stride,struct fwnode_handle * handle)1733 static int __init gic_init_bases(void __iomem *dist_base,
1734 struct redist_region *rdist_regs,
1735 u32 nr_redist_regions,
1736 u64 redist_stride,
1737 struct fwnode_handle *handle)
1738 {
1739 u32 typer;
1740 int err;
1741
1742 if (!is_hyp_mode_available())
1743 static_branch_disable(&supports_deactivate_key);
1744
1745 if (static_branch_likely(&supports_deactivate_key))
1746 pr_info("GIC: Using split EOI/Deactivate mode\n");
1747
1748 gic_data.fwnode = handle;
1749 gic_data.dist_base = dist_base;
1750 gic_data.redist_regions = rdist_regs;
1751 gic_data.nr_redist_regions = nr_redist_regions;
1752 gic_data.redist_stride = redist_stride;
1753
1754 /*
1755 * Find out how many interrupts are supported.
1756 */
1757 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1758 gic_data.rdists.gicd_typer = typer;
1759
1760 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1761 gic_quirks, &gic_data);
1762
1763 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1764 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1765
1766 /*
1767 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1768 * architecture spec (which says that reserved registers are RES0).
1769 */
1770 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1771 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1772
1773 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1774 &gic_data);
1775 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1776 gic_data.rdists.has_rvpeid = true;
1777 gic_data.rdists.has_vlpis = true;
1778 gic_data.rdists.has_direct_lpi = true;
1779 gic_data.rdists.has_vpend_valid_dirty = true;
1780
1781 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1782 err = -ENOMEM;
1783 goto out_free;
1784 }
1785
1786 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1787
1788 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1789 pr_info("Distributor has %sRange Selector support\n",
1790 gic_data.has_rss ? "" : "no ");
1791
1792 if (typer & GICD_TYPER_MBIS) {
1793 err = mbi_init(handle, gic_data.domain);
1794 if (err)
1795 pr_err("Failed to initialize MBIs\n");
1796 }
1797
1798 set_handle_irq(gic_handle_irq);
1799
1800 gic_update_rdist_properties();
1801
1802 gic_dist_init();
1803 gic_cpu_init();
1804 gic_smp_init();
1805 gic_cpu_pm_init();
1806 gic_syscore_init();
1807
1808 if (gic_dist_supports_lpis()) {
1809 its_init(handle, &gic_data.rdists, gic_data.domain);
1810 its_cpu_init();
1811 } else {
1812 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1813 gicv2m_init(handle, gic_data.domain);
1814 }
1815
1816 gic_enable_nmi_support();
1817
1818 return 0;
1819
1820 out_free:
1821 if (gic_data.domain)
1822 irq_domain_remove(gic_data.domain);
1823 free_percpu(gic_data.rdists.rdist);
1824 return err;
1825 }
1826
gic_validate_dist_version(void __iomem * dist_base)1827 static int __init gic_validate_dist_version(void __iomem *dist_base)
1828 {
1829 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1830
1831 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1832 return -ENODEV;
1833
1834 return 0;
1835 }
1836
1837 /* Create all possible partitions at boot time */
gic_populate_ppi_partitions(struct device_node * gic_node)1838 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1839 {
1840 struct device_node *parts_node, *child_part;
1841 int part_idx = 0, i;
1842 int nr_parts;
1843 struct partition_affinity *parts;
1844
1845 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1846 if (!parts_node)
1847 return;
1848
1849 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
1850 if (!gic_data.ppi_descs)
1851 goto out_put_node;
1852
1853 nr_parts = of_get_child_count(parts_node);
1854
1855 if (!nr_parts)
1856 goto out_put_node;
1857
1858 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1859 if (WARN_ON(!parts))
1860 goto out_put_node;
1861
1862 for_each_child_of_node(parts_node, child_part) {
1863 struct partition_affinity *part;
1864 int n;
1865
1866 part = &parts[part_idx];
1867
1868 part->partition_id = of_node_to_fwnode(child_part);
1869
1870 pr_info("GIC: PPI partition %pOFn[%d] { ",
1871 child_part, part_idx);
1872
1873 n = of_property_count_elems_of_size(child_part, "affinity",
1874 sizeof(u32));
1875 WARN_ON(n <= 0);
1876
1877 for (i = 0; i < n; i++) {
1878 int err, cpu;
1879 u32 cpu_phandle;
1880 struct device_node *cpu_node;
1881
1882 err = of_property_read_u32_index(child_part, "affinity",
1883 i, &cpu_phandle);
1884 if (WARN_ON(err))
1885 continue;
1886
1887 cpu_node = of_find_node_by_phandle(cpu_phandle);
1888 if (WARN_ON(!cpu_node))
1889 continue;
1890
1891 cpu = of_cpu_node_to_id(cpu_node);
1892 if (WARN_ON(cpu < 0)) {
1893 of_node_put(cpu_node);
1894 continue;
1895 }
1896
1897 pr_cont("%pOF[%d] ", cpu_node, cpu);
1898
1899 cpumask_set_cpu(cpu, &part->mask);
1900 of_node_put(cpu_node);
1901 }
1902
1903 pr_cont("}\n");
1904 part_idx++;
1905 }
1906
1907 for (i = 0; i < gic_data.ppi_nr; i++) {
1908 unsigned int irq;
1909 struct partition_desc *desc;
1910 struct irq_fwspec ppi_fwspec = {
1911 .fwnode = gic_data.fwnode,
1912 .param_count = 3,
1913 .param = {
1914 [0] = GIC_IRQ_TYPE_PARTITION,
1915 [1] = i,
1916 [2] = IRQ_TYPE_NONE,
1917 },
1918 };
1919
1920 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1921 if (WARN_ON(!irq))
1922 continue;
1923 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1924 irq, &partition_domain_ops);
1925 if (WARN_ON(!desc))
1926 continue;
1927
1928 gic_data.ppi_descs[i] = desc;
1929 }
1930
1931 out_put_node:
1932 of_node_put(parts_node);
1933 }
1934
gic_of_setup_kvm_info(struct device_node * node)1935 static void __init gic_of_setup_kvm_info(struct device_node *node)
1936 {
1937 int ret;
1938 struct resource r;
1939 u32 gicv_idx;
1940
1941 gic_v3_kvm_info.type = GIC_V3;
1942
1943 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1944 if (!gic_v3_kvm_info.maint_irq)
1945 return;
1946
1947 if (of_property_read_u32(node, "#redistributor-regions",
1948 &gicv_idx))
1949 gicv_idx = 1;
1950
1951 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
1952 ret = of_address_to_resource(node, gicv_idx, &r);
1953 if (!ret)
1954 gic_v3_kvm_info.vcpu = r;
1955
1956 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1957 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
1958 gic_set_kvm_info(&gic_v3_kvm_info);
1959 }
1960
gic_of_init(struct device_node * node,struct device_node * parent)1961 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1962 {
1963 void __iomem *dist_base;
1964 struct redist_region *rdist_regs;
1965 u64 redist_stride;
1966 u32 nr_redist_regions;
1967 int err, i;
1968
1969 dist_base = of_iomap(node, 0);
1970 if (!dist_base) {
1971 pr_err("%pOF: unable to map gic dist registers\n", node);
1972 return -ENXIO;
1973 }
1974
1975 err = gic_validate_dist_version(dist_base);
1976 if (err) {
1977 pr_err("%pOF: no distributor detected, giving up\n", node);
1978 goto out_unmap_dist;
1979 }
1980
1981 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1982 nr_redist_regions = 1;
1983
1984 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1985 GFP_KERNEL);
1986 if (!rdist_regs) {
1987 err = -ENOMEM;
1988 goto out_unmap_dist;
1989 }
1990
1991 for (i = 0; i < nr_redist_regions; i++) {
1992 struct resource res;
1993 int ret;
1994
1995 ret = of_address_to_resource(node, 1 + i, &res);
1996 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1997 if (ret || !rdist_regs[i].redist_base) {
1998 pr_err("%pOF: couldn't map region %d\n", node, i);
1999 err = -ENODEV;
2000 goto out_unmap_rdist;
2001 }
2002 rdist_regs[i].phys_base = res.start;
2003 }
2004
2005 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
2006 redist_stride = 0;
2007
2008 gic_enable_of_quirks(node, gic_quirks, &gic_data);
2009
2010 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
2011 redist_stride, &node->fwnode);
2012 if (err)
2013 goto out_unmap_rdist;
2014
2015 gic_populate_ppi_partitions(node);
2016
2017 if (static_branch_likely(&supports_deactivate_key))
2018 gic_of_setup_kvm_info(node);
2019 return 0;
2020
2021 out_unmap_rdist:
2022 for (i = 0; i < nr_redist_regions; i++)
2023 if (rdist_regs[i].redist_base)
2024 iounmap(rdist_regs[i].redist_base);
2025 kfree(rdist_regs);
2026 out_unmap_dist:
2027 iounmap(dist_base);
2028 return err;
2029 }
2030
2031 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2032
2033 #ifdef CONFIG_ACPI
2034 static struct
2035 {
2036 void __iomem *dist_base;
2037 struct redist_region *redist_regs;
2038 u32 nr_redist_regions;
2039 bool single_redist;
2040 int enabled_rdists;
2041 u32 maint_irq;
2042 int maint_irq_mode;
2043 phys_addr_t vcpu_base;
2044 } acpi_data __initdata;
2045
2046 static void __init
gic_acpi_register_redist(phys_addr_t phys_base,void __iomem * redist_base)2047 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
2048 {
2049 static int count = 0;
2050
2051 acpi_data.redist_regs[count].phys_base = phys_base;
2052 acpi_data.redist_regs[count].redist_base = redist_base;
2053 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
2054 count++;
2055 }
2056
2057 static int __init
gic_acpi_parse_madt_redist(union acpi_subtable_headers * header,const unsigned long end)2058 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
2059 const unsigned long end)
2060 {
2061 struct acpi_madt_generic_redistributor *redist =
2062 (struct acpi_madt_generic_redistributor *)header;
2063 void __iomem *redist_base;
2064
2065 redist_base = ioremap(redist->base_address, redist->length);
2066 if (!redist_base) {
2067 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
2068 return -ENOMEM;
2069 }
2070
2071 gic_acpi_register_redist(redist->base_address, redist_base);
2072 return 0;
2073 }
2074
2075 static int __init
gic_acpi_parse_madt_gicc(union acpi_subtable_headers * header,const unsigned long end)2076 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
2077 const unsigned long end)
2078 {
2079 struct acpi_madt_generic_interrupt *gicc =
2080 (struct acpi_madt_generic_interrupt *)header;
2081 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
2082 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
2083 void __iomem *redist_base;
2084
2085 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
2086 if (!(gicc->flags & ACPI_MADT_ENABLED))
2087 return 0;
2088
2089 redist_base = ioremap(gicc->gicr_base_address, size);
2090 if (!redist_base)
2091 return -ENOMEM;
2092
2093 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
2094 return 0;
2095 }
2096
gic_acpi_collect_gicr_base(void)2097 static int __init gic_acpi_collect_gicr_base(void)
2098 {
2099 acpi_tbl_entry_handler redist_parser;
2100 enum acpi_madt_type type;
2101
2102 if (acpi_data.single_redist) {
2103 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
2104 redist_parser = gic_acpi_parse_madt_gicc;
2105 } else {
2106 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
2107 redist_parser = gic_acpi_parse_madt_redist;
2108 }
2109
2110 /* Collect redistributor base addresses in GICR entries */
2111 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
2112 return 0;
2113
2114 pr_info("No valid GICR entries exist\n");
2115 return -ENODEV;
2116 }
2117
gic_acpi_match_gicr(union acpi_subtable_headers * header,const unsigned long end)2118 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
2119 const unsigned long end)
2120 {
2121 /* Subtable presence means that redist exists, that's it */
2122 return 0;
2123 }
2124
gic_acpi_match_gicc(union acpi_subtable_headers * header,const unsigned long end)2125 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
2126 const unsigned long end)
2127 {
2128 struct acpi_madt_generic_interrupt *gicc =
2129 (struct acpi_madt_generic_interrupt *)header;
2130
2131 /*
2132 * If GICC is enabled and has valid gicr base address, then it means
2133 * GICR base is presented via GICC
2134 */
2135 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
2136 acpi_data.enabled_rdists++;
2137 return 0;
2138 }
2139
2140 /*
2141 * It's perfectly valid firmware can pass disabled GICC entry, driver
2142 * should not treat as errors, skip the entry instead of probe fail.
2143 */
2144 if (!(gicc->flags & ACPI_MADT_ENABLED))
2145 return 0;
2146
2147 return -ENODEV;
2148 }
2149
gic_acpi_count_gicr_regions(void)2150 static int __init gic_acpi_count_gicr_regions(void)
2151 {
2152 int count;
2153
2154 /*
2155 * Count how many redistributor regions we have. It is not allowed
2156 * to mix redistributor description, GICR and GICC subtables have to be
2157 * mutually exclusive.
2158 */
2159 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
2160 gic_acpi_match_gicr, 0);
2161 if (count > 0) {
2162 acpi_data.single_redist = false;
2163 return count;
2164 }
2165
2166 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2167 gic_acpi_match_gicc, 0);
2168 if (count > 0) {
2169 acpi_data.single_redist = true;
2170 count = acpi_data.enabled_rdists;
2171 }
2172
2173 return count;
2174 }
2175
acpi_validate_gic_table(struct acpi_subtable_header * header,struct acpi_probe_entry * ape)2176 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2177 struct acpi_probe_entry *ape)
2178 {
2179 struct acpi_madt_generic_distributor *dist;
2180 int count;
2181
2182 dist = (struct acpi_madt_generic_distributor *)header;
2183 if (dist->version != ape->driver_data)
2184 return false;
2185
2186 /* We need to do that exercise anyway, the sooner the better */
2187 count = gic_acpi_count_gicr_regions();
2188 if (count <= 0)
2189 return false;
2190
2191 acpi_data.nr_redist_regions = count;
2192 return true;
2193 }
2194
gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers * header,const unsigned long end)2195 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
2196 const unsigned long end)
2197 {
2198 struct acpi_madt_generic_interrupt *gicc =
2199 (struct acpi_madt_generic_interrupt *)header;
2200 int maint_irq_mode;
2201 static int first_madt = true;
2202
2203 /* Skip unusable CPUs */
2204 if (!(gicc->flags & ACPI_MADT_ENABLED))
2205 return 0;
2206
2207 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2208 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2209
2210 if (first_madt) {
2211 first_madt = false;
2212
2213 acpi_data.maint_irq = gicc->vgic_interrupt;
2214 acpi_data.maint_irq_mode = maint_irq_mode;
2215 acpi_data.vcpu_base = gicc->gicv_base_address;
2216
2217 return 0;
2218 }
2219
2220 /*
2221 * The maintenance interrupt and GICV should be the same for every CPU
2222 */
2223 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2224 (acpi_data.maint_irq_mode != maint_irq_mode) ||
2225 (acpi_data.vcpu_base != gicc->gicv_base_address))
2226 return -EINVAL;
2227
2228 return 0;
2229 }
2230
gic_acpi_collect_virt_info(void)2231 static bool __init gic_acpi_collect_virt_info(void)
2232 {
2233 int count;
2234
2235 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2236 gic_acpi_parse_virt_madt_gicc, 0);
2237
2238 return (count > 0);
2239 }
2240
2241 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
2242 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
2243 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
2244
gic_acpi_setup_kvm_info(void)2245 static void __init gic_acpi_setup_kvm_info(void)
2246 {
2247 int irq;
2248
2249 if (!gic_acpi_collect_virt_info()) {
2250 pr_warn("Unable to get hardware information used for virtualization\n");
2251 return;
2252 }
2253
2254 gic_v3_kvm_info.type = GIC_V3;
2255
2256 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2257 acpi_data.maint_irq_mode,
2258 ACPI_ACTIVE_HIGH);
2259 if (irq <= 0)
2260 return;
2261
2262 gic_v3_kvm_info.maint_irq = irq;
2263
2264 if (acpi_data.vcpu_base) {
2265 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2266
2267 vcpu->flags = IORESOURCE_MEM;
2268 vcpu->start = acpi_data.vcpu_base;
2269 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2270 }
2271
2272 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2273 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2274 gic_set_kvm_info(&gic_v3_kvm_info);
2275 }
2276
2277 static int __init
gic_acpi_init(union acpi_subtable_headers * header,const unsigned long end)2278 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
2279 {
2280 struct acpi_madt_generic_distributor *dist;
2281 struct fwnode_handle *domain_handle;
2282 size_t size;
2283 int i, err;
2284
2285 /* Get distributor base address */
2286 dist = (struct acpi_madt_generic_distributor *)header;
2287 acpi_data.dist_base = ioremap(dist->base_address,
2288 ACPI_GICV3_DIST_MEM_SIZE);
2289 if (!acpi_data.dist_base) {
2290 pr_err("Unable to map GICD registers\n");
2291 return -ENOMEM;
2292 }
2293
2294 err = gic_validate_dist_version(acpi_data.dist_base);
2295 if (err) {
2296 pr_err("No distributor detected at @%p, giving up\n",
2297 acpi_data.dist_base);
2298 goto out_dist_unmap;
2299 }
2300
2301 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2302 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2303 if (!acpi_data.redist_regs) {
2304 err = -ENOMEM;
2305 goto out_dist_unmap;
2306 }
2307
2308 err = gic_acpi_collect_gicr_base();
2309 if (err)
2310 goto out_redist_unmap;
2311
2312 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
2313 if (!domain_handle) {
2314 err = -ENOMEM;
2315 goto out_redist_unmap;
2316 }
2317
2318 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
2319 acpi_data.nr_redist_regions, 0, domain_handle);
2320 if (err)
2321 goto out_fwhandle_free;
2322
2323 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
2324
2325 if (static_branch_likely(&supports_deactivate_key))
2326 gic_acpi_setup_kvm_info();
2327
2328 return 0;
2329
2330 out_fwhandle_free:
2331 irq_domain_free_fwnode(domain_handle);
2332 out_redist_unmap:
2333 for (i = 0; i < acpi_data.nr_redist_regions; i++)
2334 if (acpi_data.redist_regs[i].redist_base)
2335 iounmap(acpi_data.redist_regs[i].redist_base);
2336 kfree(acpi_data.redist_regs);
2337 out_dist_unmap:
2338 iounmap(acpi_data.dist_base);
2339 return err;
2340 }
2341 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2342 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2343 gic_acpi_init);
2344 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2345 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2346 gic_acpi_init);
2347 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2348 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
2349 gic_acpi_init);
2350 #endif
2351