1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/arm/pmu.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ARM Performance Monitor Units 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Mark Rutland <mark.rutland@arm.com> 11*4882a593Smuzhiyun - Will Deacon <will.deacon@arm.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: |+ 14*4882a593Smuzhiyun ARM cores often have a PMU for counting cpu and cache events like cache misses 15*4882a593Smuzhiyun and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU 16*4882a593Smuzhiyun representation in the device tree should be done as under:- 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun items: 21*4882a593Smuzhiyun - enum: 22*4882a593Smuzhiyun - apm,potenza-pmu 23*4882a593Smuzhiyun - arm,armv8-pmuv3 # Only for s/w models 24*4882a593Smuzhiyun - arm,arm1136-pmu 25*4882a593Smuzhiyun - arm,arm1176-pmu 26*4882a593Smuzhiyun - arm,arm11mpcore-pmu 27*4882a593Smuzhiyun - arm,cortex-a5-pmu 28*4882a593Smuzhiyun - arm,cortex-a7-pmu 29*4882a593Smuzhiyun - arm,cortex-a8-pmu 30*4882a593Smuzhiyun - arm,cortex-a9-pmu 31*4882a593Smuzhiyun - arm,cortex-a12-pmu 32*4882a593Smuzhiyun - arm,cortex-a15-pmu 33*4882a593Smuzhiyun - arm,cortex-a17-pmu 34*4882a593Smuzhiyun - arm,cortex-a32-pmu 35*4882a593Smuzhiyun - arm,cortex-a34-pmu 36*4882a593Smuzhiyun - arm,cortex-a35-pmu 37*4882a593Smuzhiyun - arm,cortex-a53-pmu 38*4882a593Smuzhiyun - arm,cortex-a55-pmu 39*4882a593Smuzhiyun - arm,cortex-a57-pmu 40*4882a593Smuzhiyun - arm,cortex-a65-pmu 41*4882a593Smuzhiyun - arm,cortex-a72-pmu 42*4882a593Smuzhiyun - arm,cortex-a73-pmu 43*4882a593Smuzhiyun - arm,cortex-a75-pmu 44*4882a593Smuzhiyun - arm,cortex-a76-pmu 45*4882a593Smuzhiyun - arm,cortex-a77-pmu 46*4882a593Smuzhiyun - arm,neoverse-e1-pmu 47*4882a593Smuzhiyun - arm,neoverse-n1-pmu 48*4882a593Smuzhiyun - brcm,vulcan-pmu 49*4882a593Smuzhiyun - cavium,thunder-pmu 50*4882a593Smuzhiyun - qcom,krait-pmu 51*4882a593Smuzhiyun - qcom,scorpion-pmu 52*4882a593Smuzhiyun - qcom,scorpion-mp-pmu 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun interrupts: 55*4882a593Smuzhiyun # Don't know how many CPUs, so no constraints to specify 56*4882a593Smuzhiyun description: 1 per-cpu interrupt (PPI) or 1 interrupt per core. 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun interrupt-affinity: 59*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle-array 60*4882a593Smuzhiyun description: 61*4882a593Smuzhiyun When using SPIs, specifies a list of phandles to CPU 62*4882a593Smuzhiyun nodes corresponding directly to the affinity of 63*4882a593Smuzhiyun the SPIs listed in the interrupts property. 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun When using a PPI, specifies a list of phandles to CPU 66*4882a593Smuzhiyun nodes corresponding to the set of CPUs which have 67*4882a593Smuzhiyun a PMU of this type signalling the PPI listed in the 68*4882a593Smuzhiyun interrupts property, unless this is already specified 69*4882a593Smuzhiyun by the PPI interrupt specifier itself (in which case 70*4882a593Smuzhiyun the interrupt-affinity property shouldn't be present). 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun This property should be present when there is more than 73*4882a593Smuzhiyun a single SPI. 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun qcom,no-pc-write: 76*4882a593Smuzhiyun type: boolean 77*4882a593Smuzhiyun description: 78*4882a593Smuzhiyun Indicates that this PMU doesn't support the 0xc and 0xd events. 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun secure-reg-access: 81*4882a593Smuzhiyun type: boolean 82*4882a593Smuzhiyun description: 83*4882a593Smuzhiyun Indicates that the ARMv7 Secure Debug Enable Register 84*4882a593Smuzhiyun (SDER) is accessible. This will cause the driver to do 85*4882a593Smuzhiyun any setup required that is only possible in ARMv7 secure 86*4882a593Smuzhiyun state. If not present the ARMv7 SDER will not be touched, 87*4882a593Smuzhiyun which means the PMU may fail to operate unless external 88*4882a593Smuzhiyun code (bootloader or security monitor) has performed the 89*4882a593Smuzhiyun appropriate initialisation. Note that this property is 90*4882a593Smuzhiyun not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux 91*4882a593Smuzhiyun in Non-secure state. 92*4882a593Smuzhiyun 93*4882a593Smuzhiyunrequired: 94*4882a593Smuzhiyun - compatible 95*4882a593Smuzhiyun 96*4882a593SmuzhiyunadditionalProperties: false 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun... 99