Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
27 #include <linux/irqchip/arm-gic-common.h>
28 #include <linux/irqchip/arm-gic-v3.h>
29 #include <linux/irqchip/irq-partition-percpu.h>
38 #include "irq-gic-common.h"
62 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
66 * When security is enabled, non-secure priority values from the (re)distributor
70 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
76 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
78 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
96 * When the Non-secure world has access to group 0 interrupts (as a
101 * written by software is moved to the Non-secure range by the Distributor.
124 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
162 return __get_intid_range(d->hwirq); in get_intid_range()
167 return d->hwirq; in gic_irq()
188 /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
193 /* SPI -> dist_base */ in gic_dist_base()
206 count--; in gic_do_wait_for_rwp()
264 while (--count) { in gic_enable_redist()
285 *index = d->hwirq; in convert_offset_index()
293 *index = d->hwirq - EPPI_BASE_INTID + 32; in convert_offset_index()
296 *index = d->hwirq - ESPI_BASE_INTID; in convert_offset_index()
325 *index = d->hwirq; in convert_offset_index()
400 u32 reg; in gic_irq_set_irqchip_state() local
402 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ in gic_irq_set_irqchip_state()
403 return -EINVAL; in gic_irq_set_irqchip_state()
407 reg = val ? GICD_ISPENDR : GICD_ICPENDR; in gic_irq_set_irqchip_state()
411 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; in gic_irq_set_irqchip_state()
415 reg = val ? GICD_ICENABLER : GICD_ISENABLER; in gic_irq_set_irqchip_state()
419 return -EINVAL; in gic_irq_set_irqchip_state()
422 gic_poke_irq(d, reg); in gic_irq_set_irqchip_state()
429 if (d->hwirq >= 8192) /* PPI/SPI only */ in gic_irq_get_irqchip_state()
430 return -EINVAL; in gic_irq_get_irqchip_state()
446 return -EINVAL; in gic_irq_get_irqchip_state()
466 return d->hwirq - 16; in gic_get_ppi_index()
468 return d->hwirq - EPPI_BASE_INTID + 16; in gic_get_ppi_index()
476 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_setup()
479 return -EINVAL; in gic_irq_nmi_setup()
482 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_setup()
483 return -EINVAL; in gic_irq_nmi_setup()
491 return -EINVAL; in gic_irq_nmi_setup()
500 desc->handle_irq = handle_percpu_devid_fasteoi_nmi; in gic_irq_nmi_setup()
503 desc->handle_irq = handle_fasteoi_nmi; in gic_irq_nmi_setup()
513 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_teardown()
519 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_teardown()
536 desc->handle_irq = handle_percpu_devid_irq; in gic_irq_nmi_teardown()
538 desc->handle_irq = handle_fasteoi_irq; in gic_irq_nmi_teardown()
573 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; in gic_set_type()
578 return -EINVAL; in gic_set_type()
593 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); in gic_set_type()
603 return -EINVAL; in gic_irq_set_vcpu_affinity()
746 * setting the highest possible, non-zero priority in PMR. in gic_has_group0()
750 * actual priority in the non-secure range. In the process, it in gic_has_group0()
753 * we're don't have access to Group0. in gic_has_group0()
755 gic_write_pmr(BIT(8 - gic_get_pribits())); in gic_has_group0()
775 * Configure SPIs as non-secure Group-1. This will only matter in gic_dist_init()
777 * do the right thing if the kernel is running in secure mode, in gic_dist_init()
824 int ret = -ENODEV; in gic_iterate_rdists()
830 u32 reg; in gic_iterate_rdists() local
832 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; in gic_iterate_rdists()
833 if (reg != GIC_PIDR2_ARCH_GICv3 && in gic_iterate_rdists()
834 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ in gic_iterate_rdists()
858 return ret ? -ENODEV : 0; in gic_iterate_rdists()
878 u64 offset = ptr - region->redist_base; in __gic_populate_rdist()
879 raw_spin_lock_init(&gic_data_rdist()->rd_lock); in __gic_populate_rdist()
881 gic_data_rdist()->phys_base = region->phys_base + offset; in __gic_populate_rdist()
885 (int)(region - gic_data.redist_regions), in __gic_populate_rdist()
886 &gic_data_rdist()->phys_base); in __gic_populate_rdist()
900 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", in gic_populate_rdist()
903 return -ENODEV; in gic_populate_rdist()
911 /* Boot-time cleanip */ in __gic_update_rdist_properties()
929 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ in __gic_update_rdist_properties()
935 /* Detect non-sensical configurations */ in __gic_update_rdist_properties()
1011 * any pre-emptive interrupts from working at all). Writing a zero in gic_cpu_sys_reg_init()
1080 * - The write is ignored. in gic_cpu_sys_reg_init()
1081 * - The RS field is treated as 0. in gic_cpu_sys_reg_init()
1120 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1163 cpu--; in gic_compute_target_list()
1195 if (WARN_ON(d->hwirq >= 16)) in gic_ipi_send_mask()
1209 gic_send_sgi(cluster_id, tlist, d->hwirq); in gic_ipi_send_mask()
1228 /* Register all 8 non-secure SGIs */ in gic_smp_init()
1229 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8, in gic_smp_init()
1243 void __iomem *reg; in gic_set_affinity() local
1253 return -EINVAL; in gic_set_affinity()
1256 return -EINVAL; in gic_set_affinity()
1264 reg = gic_dist_base(d) + offset + (index * 8); in gic_set_affinity()
1268 gic_write_irouter(val, reg); in gic_set_affinity()
1393 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1401 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1407 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1415 return -EPERM; in gic_irq_domain_map()
1416 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1421 return -EPERM; in gic_irq_domain_map()
1434 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { in gic_irq_domain_translate()
1435 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1440 if (is_of_node(fwspec->fwnode)) { in gic_irq_domain_translate()
1441 if (fwspec->param_count < 3) in gic_irq_domain_translate()
1442 return -EINVAL; in gic_irq_domain_translate()
1444 switch (fwspec->param[0]) { in gic_irq_domain_translate()
1446 *hwirq = fwspec->param[1] + 32; in gic_irq_domain_translate()
1449 *hwirq = fwspec->param[1] + 16; in gic_irq_domain_translate()
1452 *hwirq = fwspec->param[1] + ESPI_BASE_INTID; in gic_irq_domain_translate()
1455 *hwirq = fwspec->param[1] + EPPI_BASE_INTID; in gic_irq_domain_translate()
1458 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1461 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1462 if (fwspec->param[1] >= 16) in gic_irq_domain_translate()
1463 *hwirq += EPPI_BASE_INTID - 16; in gic_irq_domain_translate()
1468 return -EINVAL; in gic_irq_domain_translate()
1471 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in gic_irq_domain_translate()
1478 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); in gic_irq_domain_translate()
1482 if (is_fwnode_irqchip(fwspec->fwnode)) { in gic_irq_domain_translate()
1483 if(fwspec->param_count != 2) in gic_irq_domain_translate()
1484 return -EINVAL; in gic_irq_domain_translate()
1486 if (fwspec->param[0] < 16) { in gic_irq_domain_translate()
1488 fwspec->param[0]); in gic_irq_domain_translate()
1489 return -EINVAL; in gic_irq_domain_translate()
1492 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1493 *type = fwspec->param[1]; in gic_irq_domain_translate()
1499 return -EINVAL; in gic_irq_domain_translate()
1540 if (fwspec->fwnode != d->fwnode) in gic_irq_domain_select()
1544 if (!is_of_node(fwspec->fwnode)) in gic_irq_domain_select()
1548 * If this is a PPI and we have a 4th (non-null) parameter, in gic_irq_domain_select()
1551 if (fwspec->param_count >= 4 && in gic_irq_domain_select()
1552 fwspec->param[0] == 1 && fwspec->param[3] != 0 && in gic_irq_domain_select()
1554 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); in gic_irq_domain_select()
1575 return -ENOMEM; in partition_domain_translate()
1577 np = of_find_node_by_phandle(fwspec->param[3]); in partition_domain_translate()
1579 return -EINVAL; in partition_domain_translate()
1581 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], in partition_domain_translate()
1587 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in partition_domain_translate()
1601 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; in gic_enable_quirk_msm8996()
1610 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; in gic_enable_quirk_cavium_38539()
1620 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite in gic_enable_quirk_hip06_07()
1622 * that GIC-600 doesn't have ESPI, so nothing to do in that case. in gic_enable_quirk_hip06_07()
1626 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { in gic_enable_quirk_hip06_07()
1628 d->rdists.gicd_typer &= ~GENMASK(9, 8); in gic_enable_quirk_hip06_07()
1638 .compatible = "qcom,msm8996-gic-v3",
1657 * - ThunderX: CN88xx
1658 * - OCTEON TX: CN83xx, CN81xx
1659 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1692 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", in gic_enable_nmi_support()
1698 * and if Group 0 interrupts can be delivered to Linux in the non-secure in gic_enable_nmi_support()
1704 * ----------------------------------------------------------- in gic_enable_nmi_support()
1705 * 1 | - | unchanged | unchanged in gic_enable_nmi_support()
1706 * ----------------------------------------------------------- in gic_enable_nmi_support()
1707 * 0 | 1 | non-secure | non-secure in gic_enable_nmi_support()
1708 * ----------------------------------------------------------- in gic_enable_nmi_support()
1709 * 0 | 0 | unchanged | non-secure in gic_enable_nmi_support()
1711 * where non-secure means that the value is right-shifted by one and the in gic_enable_nmi_support()
1712 * MSB bit set, to make it fit in the non-secure priority range. in gic_enable_nmi_support()
1719 * be in the non-secure range, we use a different PMR value to mask IRQs in gic_enable_nmi_support()
1763 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); in gic_init_bases()
1782 err = -ENOMEM; in gic_init_bases()
1829 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; in gic_validate_dist_version() local
1831 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) in gic_validate_dist_version()
1832 return -ENODEV; in gic_validate_dist_version()
1845 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); in gic_populate_ppi_partitions()
1868 part->partition_id = of_node_to_fwnode(child_part); in gic_populate_ppi_partitions()
1899 cpumask_set_cpu(cpu, &part->mask); in gic_populate_ppi_partitions()
1947 if (of_property_read_u32(node, "#redistributor-regions", in gic_of_setup_kvm_info()
1972 return -ENXIO; in gic_of_init()
1981 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) in gic_of_init()
1987 err = -ENOMEM; in gic_of_init()
1999 err = -ENODEV; in gic_of_init()
2005 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) in gic_of_init()
2011 redist_stride, &node->fwnode); in gic_of_init()
2031 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2065 redist_base = ioremap(redist->base_address, redist->length); in gic_acpi_parse_madt_redist()
2067 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
2068 return -ENOMEM; in gic_acpi_parse_madt_redist()
2071 gic_acpi_register_redist(redist->base_address, redist_base); in gic_acpi_parse_madt_redist()
2081 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; in gic_acpi_parse_madt_gicc() local
2082 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; in gic_acpi_parse_madt_gicc()
2086 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_madt_gicc()
2089 redist_base = ioremap(gicc->gicr_base_address, size); in gic_acpi_parse_madt_gicc()
2091 return -ENOMEM; in gic_acpi_parse_madt_gicc()
2093 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); in gic_acpi_parse_madt_gicc()
2115 return -ENODEV; in gic_acpi_collect_gicr_base()
2135 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { in gic_acpi_match_gicc()
2144 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_match_gicc()
2147 return -ENODEV; in gic_acpi_match_gicc()
2183 if (dist->version != ape->driver_data) in acpi_validate_gic_table()
2204 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_virt_madt_gicc()
2207 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? in gic_acpi_parse_virt_madt_gicc()
2213 acpi_data.maint_irq = gicc->vgic_interrupt; in gic_acpi_parse_virt_madt_gicc()
2215 acpi_data.vcpu_base = gicc->gicv_base_address; in gic_acpi_parse_virt_madt_gicc()
2223 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || in gic_acpi_parse_virt_madt_gicc()
2225 (acpi_data.vcpu_base != gicc->gicv_base_address)) in gic_acpi_parse_virt_madt_gicc()
2226 return -EINVAL; in gic_acpi_parse_virt_madt_gicc()
2267 vcpu->flags = IORESOURCE_MEM; in gic_acpi_setup_kvm_info()
2268 vcpu->start = acpi_data.vcpu_base; in gic_acpi_setup_kvm_info()
2269 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; in gic_acpi_setup_kvm_info()
2287 acpi_data.dist_base = ioremap(dist->base_address, in gic_acpi_init()
2291 return -ENOMEM; in gic_acpi_init()
2304 err = -ENOMEM; in gic_acpi_init()
2312 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); in gic_acpi_init()
2314 err = -ENOMEM; in gic_acpi_init()