| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/mvl88w8977/mlan/ |
| H A D | mlan_sdio.h | 39 /* Host Control Registers */
40 /** Host Control Registers : Host to Card Event */
42 /** Host Control Registers : Host terminates Command 53 */
44 /** Host Control Registers : Host without Command 53 finish host */
46 /** Host Control Registers : Host power up */
48 /** Host Control Registers : Host power down */
51 /** Host Control Registers : Host interrupt RSR */
54 /** Host Control Registers : Upload host interrupt RSR */
58 /** Host Control Registers : Host interrupt mask */
61 /** Host Control Registers : Upload host interrupt mask */
[all …]
|
| /OK3568_Linux_fs/kernel/sound/soc/ux500/ |
| H A D | ux500_msp_i2s.c | 141 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
169 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
209 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
225 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
226 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
258 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
264 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| H A D | cpu.h | 13 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
14 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
15 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
16 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
17 #define DMA_BASE 0x31000000 /* DMA controller registers base */
18 #define USB_BASE 0x31020000 /* USB registers base */
19 #define LCD_BASE 0x31040000 /* LCD registers base */
20 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
21 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
24 #define CLK_PM_BASE 0x40004000 /* System control registers base */
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_gpuprops_backend.c | 36 struct kbase_gpuprops_regdump registers = { 0 }; in kbase_backend_gpuprops_get() local
38 /* Fill regdump with the content of the relevant registers */ in kbase_backend_gpuprops_get()
39 registers.gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_backend_gpuprops_get()
41 registers.l2_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
44 registers.tiler_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
46 registers.mem_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
48 registers.mmu_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
50 registers.as_present = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
53 registers.js_present = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
56 registers.js_present = 0; in kbase_backend_gpuprops_get()
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/trace/coresight/ |
| H A D | coresight-etm4x-reference.rst | 17 ETMv4 registers that they effect. Note the register names are given without
23 :Trace Registers: {CONFIGR + others}
27 other registers to enable the features requested.
40 :Trace Registers: All
50 :Trace Registers: PRGCTLR, All hardware regs.
63 :Trace Registers: None.
75 :Trace Registers: None.
88 :Trace Registers: ACVR[idx, idx+1], VIIECTLR
111 :Trace Registers: ACVR[idx]
124 :Trace Registers: ACVR[idx], VISSCTLR
[all …]
|
| /OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/share/doc/gdb/ |
| H A D | Registers.html | 17 <title>Debugging with GDB: Registers</title>
19 <meta name="description" content="Debugging with GDB: Registers">
20 <meta name="keywords" content="Debugging with GDB: Registers">
64 <a name="Registers"></a>
70 <a name="Registers-1"></a>
71 <h3 class="section">10.13 Registers</h3>
73 <a name="index-registers"></a>
75 with names starting with ‘<samp>$</samp>’. The names of registers are different
76 for each machine; use <code>info registers</code> to see the names used on
80 <dd><a name="index-info-registers"></a>
[all …]
|
| H A D | PowerPC-Features.html | 75 targets. It should contain registers ‘<samp>r0</samp>’ through ‘<samp>r31</samp>…
80 contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’ and ‘<…
83 contain registers ‘<samp>vr0</samp>’ through ‘<samp>vr31</samp>’, ‘<s…
84 ‘<samp>vrsave</samp>’. <small>GDB</small> will define pseudo-registers ‘<samp>v0…
86 registers.
89 contain registers ‘<samp>vs0h</samp>’ through ‘<samp>vs31h</samp>’. <small…
90 combine these registers with the floating point registers (‘<samp>f0</samp>’
91 through ‘<samp>f31</samp>’) and the altivec registers (‘<samp>vr0</samp>’ t…
92 ‘<samp>vr31</samp>’) to present the 128-bit wide registers ‘<samp>vs0</samp>&rsqu…
93 ‘<samp>vs63</samp>’, the set of vector-scalar registers for POWER7.
[all …]
|
| /OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/share/doc/gdb/ |
| H A D | Registers.html | 17 <title>Debugging with GDB: Registers</title>
19 <meta name="description" content="Debugging with GDB: Registers">
20 <meta name="keywords" content="Debugging with GDB: Registers">
64 <a name="Registers"></a>
70 <a name="Registers-1"></a>
71 <h3 class="section">10.13 Registers</h3>
73 <a name="index-registers"></a>
75 with names starting with ‘<samp>$</samp>’. The names of registers are different
76 for each machine; use <code>info registers</code> to see the names used on
80 <dd><a name="index-info-registers"></a>
[all …]
|
| H A D | PowerPC-Features.html | 75 targets. It should contain registers ‘<samp>r0</samp>’ through ‘<samp>r31</samp>…
80 contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’ and ‘<…
83 contain registers ‘<samp>vr0</samp>’ through ‘<samp>vr31</samp>’, ‘<s…
84 ‘<samp>vrsave</samp>’. <small>GDB</small> will define pseudo-registers ‘<samp>v0…
86 registers.
89 contain registers ‘<samp>vs0h</samp>’ through ‘<samp>vs31h</samp>’. <small…
90 combine these registers with the floating point registers (‘<samp>f0</samp>’
91 through ‘<samp>f31</samp>’) and the altivec registers (‘<samp>vr0</samp>’ t…
92 ‘<samp>vr31</samp>’) to present the 128-bit wide registers ‘<samp>vs0</samp>&rsqu…
93 ‘<samp>vs63</samp>’, the set of vector-scalar registers for POWER7.
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/nxp/mlan/ |
| H A D | mlan_sdio.h | 40 /* Host Control Registers */
41 /** Host Control Registers : Host to Card Event */
43 /** Host Control Registers : Host terminates Command 53 */
45 /** Host Control Registers : Host without Command 53 finish host */
47 /** Host Control Registers : Host power up */
49 /** Host Control Registers : Host power down */
52 /** Host Control Registers : Upload host interrupt RSR */
56 /** Host Control Registers : Upload command port host interrupt status */
58 /** Host Control Registers : Download command port host interrupt status */
61 /** Host Control Registers : Upload host interrupt mask */
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/video/fbdev/i810/ |
| H A D | i810_regs.h | 25 * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers
32 /* Instruction and Interrupt Control Registers (01000h 02FFFh) */
60 /* Memory Control Registers (03000h 03FFFh) */
66 /* Span Cursor Registers (04000h 04FFFh) */
69 /* I/O Control Registers (05000h 05FFFh) */
75 /* Clock Control and Power Management Registers (06000h 06FFFh) */
86 /* Overlay Registers (30000h 03FFFFh) */
146 /* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */
158 /* Display and Cursor Control Registers (70000h 7FFFFh) */
172 /* VGA Registers */
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/lib/ |
| H A D | stacktrace.c | 72 uint32_t registers[16]; member
226 ulong vsp = state->registers[SP]; in unwind_exec_insn()
234 state->registers[SP] += ((insn & INSN_VSP_SIZE_MASK) << 2) + 4; in unwind_exec_insn()
237 state->registers[SP] -= ((insn & INSN_VSP_SIZE_MASK) << 2) + 4; in unwind_exec_insn()
255 /* Load the registers */ in unwind_exec_insn()
258 if (!pop_vsp(&state->registers[reg], &vsp, in unwind_exec_insn()
273 state->registers[SP] = in unwind_exec_insn()
274 state->registers[insn & INSN_STD_DATA_MASK]; in unwind_exec_insn()
279 /* Read how many registers to load */ in unwind_exec_insn()
285 /* Pop the registers */ in unwind_exec_insn()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/media/usb/cpia2/ |
| H A D | cpia2_core.c | 247 cmd.buffer.registers[0].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
248 cmd.buffer.registers[0].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
250 cmd.buffer.registers[1].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
251 cmd.buffer.registers[1].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
260 cmd.buffer.registers[0].index = in cpia2_do_command()
262 cmd.buffer.registers[1].index = in cpia2_do_command()
264 cmd.buffer.registers[0].value = CPIA2_SYSTEM_CONTROL_CLEAR_ERR; in cpia2_do_command()
265 cmd.buffer.registers[1].value = in cpia2_do_command()
380 cmd.buffer.registers[0].index = CPIA2_VC_VC_TARGET_KB; in cpia2_do_command()
381 cmd.buffer.registers[0].value = param; in cpia2_do_command()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/scsi/smartpqi/ |
| H A D | smartpqi_sis.c | 90 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
96 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
131 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_is_firmware_running()
141 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
148 return readl(&ctrl_info->registers->sis_firmware_status) & in sis_is_kernel_up()
160 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
166 registers = ctrl_info->registers; in sis_send_sync_cmd()
169 writel(cmd, ®isters->sis_mailbox[0]); in sis_send_sync_cmd()
176 writel(params->mailbox[i], ®isters->sis_mailbox[i]); in sis_send_sync_cmd()
180 ®isters->sis_ctrl_to_host_doorbell_clear); in sis_send_sync_cmd()
[all …]
|
| /OK3568_Linux_fs/kernel/sound/soc/codecs/ |
| H A D | tlv320aic3x.h | 44 /* ADC PGA Gain control registers */
47 /* MIC3 control registers */
50 /* Line1 Input control registers */
55 /* Line2 Input control registers */
61 /* AGC Control Registers A, B, C */
69 /* DAC Power and Left High Power Output control registers */
72 /* Right High Power Output control registers */
76 /* DAC Output Switching control registers */
78 /* High Power Output Driver Pop Reduction registers */
80 /* DAC Digital control registers */
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/ |
| H A D | mpc8349_pci.h | 10 /* Bit definitions for PCIBR registers */
14 /* Bit definitions for PCIMSK registers */
38 * Outbound ATU registers (3 sets). These registers control how 60x bus
43 #define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
47 #define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
51 #define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
55 /* Bit definitions for POMCR registers */
86 /* Bit definitions for PCI_GCR registers */
91 * Inbound ATU registers (2 sets). These registers control how PCI
103 /* Bit definitions for PCI Inbound Comparison Mask registers */
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/xtensa/include/asm/arch-de212/ |
| H A D | tie-asm.h | 38 * (not including zero-overhead loop registers).
42 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
43 * registers are clobbered, the remaining are unused).
50 * select Select what category(ies) of registers to store, as a bitmask
51 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
52 * alloc Select what category(ies) of registers to allocate; if any
54 * the corresponding registers is skipped without doing any store.
58 // Optional caller-saved registers used by default by the compiler:
70 // Optional caller-saved registers not used by default by the compiler:
92 * (not including zero-overhead loop registers).
[all …]
|
| /OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/share/doc/as.html/ |
| H A D | Blackfin-Syntax.html | 123 Register pairs are always data registers and are denoted using a colon,
128 adjacent registers. Adjacent registers are denoted in the syntax by
134 letter denoting the desired portion. For 32-bit registers, ".H"
136 least-significant portion. The subdivisions of the 40-bit registers
141 <dd><p>The set of 40-bit registers A1 and A0 that normally contain data that
149 <dd><p>The registers are designated as A1.W or A0.W.
151 <dt><code>two 16-bit registers</code></dt>
152 <dd><p>The registers are designated as A1.H, A1.L, A0.H or A0.L.
155 <dd><p>The registers are designated as A1.X or A0.X for the bits that
161 <dt><code>Data Registers</code></dt>
[all …]
|
| /OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/share/doc/as.html/ |
| H A D | Blackfin-Syntax.html | 123 Register pairs are always data registers and are denoted using a colon,
128 adjacent registers. Adjacent registers are denoted in the syntax by
134 letter denoting the desired portion. For 32-bit registers, ".H"
136 least-significant portion. The subdivisions of the 40-bit registers
141 <dd><p>The set of 40-bit registers A1 and A0 that normally contain data that
149 <dd><p>The registers are designated as A1.W or A0.W.
151 <dt><code>two 16-bit registers</code></dt>
152 <dd><p>The registers are designated as A1.H, A1.L, A0.H or A0.L.
155 <dd><p>The registers are designated as A1.X or A0.X for the bits that
161 <dt><code>Data Registers</code></dt>
[all …]
|
| H A D | i386_002dRegs.html | 72 <a name="index-i386-registers"></a>
74 <a name="index-x86_002d64-registers"></a>
76 <p>Register operands are always prefixed with ‘<samp>%</samp>’. The 80386 registers
80 <li> the 8 32-bit registers ‘<samp>%eax</samp>’ (the accumulator), ‘<samp>%ebx</s…
87 </li><li> the 8 8-bit registers: ‘<samp>%ah</samp>’, ‘<samp>%al</samp>’, &l…
92 </li><li> the 6 section registers ‘<samp>%cs</samp>’ (code section), ‘<samp>%ds</…
96 </li><li> the 5 processor control registers ‘<samp>%cr0</samp>’, ‘<samp>%cr2</sam…
99 </li><li> the 6 debug registers ‘<samp>%db0</samp>’, ‘<samp>%db1</samp>’, &…
102 </li><li> the 2 test registers ‘<samp>%tr6</samp>’ and ‘<samp>%tr7</samp>’.
107 These registers are overloaded by 8 MMX registers ‘<samp>%mm0</samp>’,
[all …]
|
| /OK3568_Linux_fs/kernel/arch/xtensa/variants/csp/include/variant/ |
| H A D | tie-asm.h | 58 * (not including zero-overhead loop registers).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
74 * the corresponding registers is skipped without doing any store.
78 // Optional global registers used by default by the compiler:
88 // Optional caller-saved registers used by default by the compiler:
100 // Optional caller-saved registers not used by default by the compiler:
[all …]
|
| /OK3568_Linux_fs/kernel/arch/xtensa/variants/de212/include/variant/ |
| H A D | tie-asm.h | 58 * (not including zero-overhead loop registers).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
74 * the corresponding registers is skipped without doing any store.
78 // Optional caller-saved registers used by default by the compiler:
90 // Optional caller-saved registers not used by default by the compiler:
112 * (not including zero-overhead loop registers).
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/xtensa/include/asm/arch-dc233c/ |
| H A D | tie-asm.h | 39 * (not including zero-overhead loop registers).
43 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
44 * registers are clobbered, the remaining are unused).
51 * select Select what category(ies) of registers to store, as a bitmask
52 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
53 * alloc Select what category(ies) of registers to allocate; if any
55 * the corresponding registers is skipped without doing any store.
69 // Optional caller-saved registers used by default by the compiler:
81 // Optional caller-saved registers not used by default by the compiler:
103 * (not including zero-overhead loop registers).
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/media/radio/si470x/ |
| H A D | radio-si470x-common.c | 185 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
186 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
203 if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE)) in si470x_set_chan()
209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
210 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
222 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
242 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
265 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
[all …]
|
| /OK3568_Linux_fs/u-boot/drivers/net/ |
| H A D | xilinx_ll_temac.h | 45 /* direct soft registers (low part) */
54 /* hard TEMAC registers */
59 /* direct soft registers (high part) */
66 /* Reset and Address Filter Registers (raf), [1] p25 */
82 /* Transmit Pause Frame Registers (tpf), [1] p28 */
86 /* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */
90 /* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */
100 /* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */
138 /* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */
144 /* VLAN TPID Word 0, 1 Registers (tpid0, tpid1), [1] p37 */
[all …]
|