1<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> 2<html> 3<!-- Copyright (C) 1988-2021 Free Software Foundation, Inc. 4 5Permission is granted to copy, distribute and/or modify this document 6under the terms of the GNU Free Documentation License, Version 1.3 or 7any later version published by the Free Software Foundation; with the 8Invariant Sections being "Free Software" and "Free Software Needs 9Free Documentation", with the Front-Cover Texts being "A GNU Manual," 10and with the Back-Cover Texts as in (a) below. 11 12(a) The FSF's Back-Cover Text is: "You are free to copy and modify 13this GNU Manual. Buying copies from GNU Press supports the FSF in 14developing GNU and promoting software freedom." --> 15<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> 16<head> 17<title>Debugging with GDB: PowerPC Features</title> 18 19<meta name="description" content="Debugging with GDB: PowerPC Features"> 20<meta name="keywords" content="Debugging with GDB: PowerPC Features"> 21<meta name="resource-type" content="document"> 22<meta name="distribution" content="global"> 23<meta name="Generator" content="makeinfo"> 24<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> 25<link href="index.html#Top" rel="start" title="Top"> 26<link href="Concept-Index.html#Concept-Index" rel="index" title="Concept Index"> 27<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> 28<link href="Standard-Target-Features.html#Standard-Target-Features" rel="up" title="Standard Target Features"> 29<link href="RISC_002dV-Features.html#RISC_002dV-Features" rel="next" title="RISC-V Features"> 30<link href="OpenRISC-1000-Features.html#OpenRISC-1000-Features" rel="previous" title="OpenRISC 1000 Features"> 31<style type="text/css"> 32<!-- 33a.summary-letter {text-decoration: none} 34blockquote.smallquotation {font-size: smaller} 35div.display {margin-left: 3.2em} 36div.example {margin-left: 3.2em} 37div.indentedblock {margin-left: 3.2em} 38div.lisp {margin-left: 3.2em} 39div.smalldisplay {margin-left: 3.2em} 40div.smallexample {margin-left: 3.2em} 41div.smallindentedblock {margin-left: 3.2em; font-size: smaller} 42div.smalllisp {margin-left: 3.2em} 43kbd {font-style:oblique} 44pre.display {font-family: inherit} 45pre.format {font-family: inherit} 46pre.menu-comment {font-family: serif} 47pre.menu-preformatted {font-family: serif} 48pre.smalldisplay {font-family: inherit; font-size: smaller} 49pre.smallexample {font-size: smaller} 50pre.smallformat {font-family: inherit; font-size: smaller} 51pre.smalllisp {font-size: smaller} 52span.nocodebreak {white-space:nowrap} 53span.nolinebreak {white-space:nowrap} 54span.roman {font-family:serif; font-weight:normal} 55span.sansserif {font-family:sans-serif; font-weight:normal} 56ul.no-bullet {list-style: none} 57--> 58</style> 59 60 61</head> 62 63<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> 64<a name="PowerPC-Features"></a> 65<div class="header"> 66<p> 67Next: <a href="RISC_002dV-Features.html#RISC_002dV-Features" accesskey="n" rel="next">RISC-V Features</a>, Previous: <a href="OpenRISC-1000-Features.html#OpenRISC-1000-Features" accesskey="p" rel="previous">OpenRISC 1000 Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p> 68</div> 69<hr> 70<a name="PowerPC-Features-1"></a> 71<h4 class="subsection">G.5.11 PowerPC Features</h4> 72<a name="index-target-descriptions_002c-PowerPC-features"></a> 73 74<p>The ‘<samp>org.gnu.gdb.power.core</samp>’ feature is required for PowerPC 75targets. It should contain registers ‘<samp>r0</samp>’ through ‘<samp>r31</samp>’, 76‘<samp>pc</samp>’, ‘<samp>msr</samp>’, ‘<samp>cr</samp>’, ‘<samp>lr</samp>’, ‘<samp>ctr</samp>’, and 77‘<samp>xer</samp>’. They may be 32-bit or 64-bit depending on the target. 78</p> 79<p>The ‘<samp>org.gnu.gdb.power.fpu</samp>’ feature is optional. It should 80contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’ and ‘<samp>fpscr</samp>’. 81</p> 82<p>The ‘<samp>org.gnu.gdb.power.altivec</samp>’ feature is optional. It should 83contain registers ‘<samp>vr0</samp>’ through ‘<samp>vr31</samp>’, ‘<samp>vscr</samp>’, and 84‘<samp>vrsave</samp>’. <small>GDB</small> will define pseudo-registers ‘<samp>v0</samp>’ 85through ‘<samp>v31</samp>’ as aliases for the corresponding ‘<samp>vrX</samp>’ 86registers. 87</p> 88<p>The ‘<samp>org.gnu.gdb.power.vsx</samp>’ feature is optional. It should 89contain registers ‘<samp>vs0h</samp>’ through ‘<samp>vs31h</samp>’. <small>GDB</small> will 90combine these registers with the floating point registers (‘<samp>f0</samp>’ 91through ‘<samp>f31</samp>’) and the altivec registers (‘<samp>vr0</samp>’ through 92‘<samp>vr31</samp>’) to present the 128-bit wide registers ‘<samp>vs0</samp>’ through 93‘<samp>vs63</samp>’, the set of vector-scalar registers for POWER7. 94Therefore, this feature requires both ‘<samp>org.gnu.gdb.power.fpu</samp>’ and 95‘<samp>org.gnu.gdb.power.altivec</samp>’. 96</p> 97<p>The ‘<samp>org.gnu.gdb.power.spe</samp>’ feature is optional. It should 98contain registers ‘<samp>ev0h</samp>’ through ‘<samp>ev31h</samp>’, ‘<samp>acc</samp>’, and 99‘<samp>spefscr</samp>’. SPE targets should provide 32-bit registers in 100‘<samp>org.gnu.gdb.power.core</samp>’ and provide the upper halves in 101‘<samp>ev0h</samp>’ through ‘<samp>ev31h</samp>’. <small>GDB</small> will combine 102these to present registers ‘<samp>ev0</samp>’ through ‘<samp>ev31</samp>’ to the 103user. 104</p> 105<p>The ‘<samp>org.gnu.gdb.power.ppr</samp>’ feature is optional. It should 106contain the 64-bit register ‘<samp>ppr</samp>’. 107</p> 108<p>The ‘<samp>org.gnu.gdb.power.dscr</samp>’ feature is optional. It should 109contain the 64-bit register ‘<samp>dscr</samp>’. 110</p> 111<p>The ‘<samp>org.gnu.gdb.power.tar</samp>’ feature is optional. It should 112contain the 64-bit register ‘<samp>tar</samp>’. 113</p> 114<p>The ‘<samp>org.gnu.gdb.power.ebb</samp>’ feature is optional. It should 115contain registers ‘<samp>bescr</samp>’, ‘<samp>ebbhr</samp>’ and ‘<samp>ebbrr</samp>’, all 11664-bit wide. 117</p> 118<p>The ‘<samp>org.gnu.gdb.power.linux.pmu</samp>’ feature is optional. It should 119contain registers ‘<samp>mmcr0</samp>’, ‘<samp>mmcr2</samp>’, ‘<samp>siar</samp>’, ‘<samp>sdar</samp>’ 120and ‘<samp>sier</samp>’, all 64-bit wide. This is the subset of the isa 2.07 121server PMU registers provided by <small>GNU</small>/Linux. 122</p> 123<p>The ‘<samp>org.gnu.gdb.power.htm.spr</samp>’ feature is optional. It should 124contain registers ‘<samp>tfhar</samp>’, ‘<samp>texasr</samp>’ and ‘<samp>tfiar</samp>’, all 12564-bit wide. 126</p> 127<p>The ‘<samp>org.gnu.gdb.power.htm.core</samp>’ feature is optional. It should 128contain the checkpointed general-purpose registers ‘<samp>cr0</samp>’ through 129‘<samp>cr31</samp>’, as well as the checkpointed registers ‘<samp>clr</samp>’ and 130‘<samp>cctr</samp>’. These registers may all be either 32-bit or 64-bit 131depending on the target. It should also contain the checkpointed 132registers ‘<samp>ccr</samp>’ and ‘<samp>cxer</samp>’, which should both be 32-bit 133wide. 134</p> 135<p>The ‘<samp>org.gnu.gdb.power.htm.fpu</samp>’ feature is optional. It should 136contain the checkpointed 64-bit floating-point registers ‘<samp>cf0</samp>’ 137through ‘<samp>cf31</samp>’, as well as the checkpointed 64-bit register 138‘<samp>cfpscr</samp>’. 139</p> 140<p>The ‘<samp>org.gnu.gdb.power.htm.altivec</samp>’ feature is optional. It 141should contain the checkpointed altivec registers ‘<samp>cvr0</samp>’ through 142‘<samp>cvr31</samp>’, all 128-bit wide. It should also contain the 143checkpointed registers ‘<samp>cvscr</samp>’ and ‘<samp>cvrsave</samp>’, both 32-bit 144wide. 145</p> 146<p>The ‘<samp>org.gnu.gdb.power.htm.vsx</samp>’ feature is optional. It should 147contain registers ‘<samp>cvs0h</samp>’ through ‘<samp>cvs31h</samp>’. <small>GDB</small> 148will combine these registers with the checkpointed floating point 149registers (‘<samp>cf0</samp>’ through ‘<samp>cf31</samp>’) and the checkpointed 150altivec registers (‘<samp>cvr0</samp>’ through ‘<samp>cvr31</samp>’) to present the 151128-bit wide checkpointed vector-scalar registers ‘<samp>cvs0</samp>’ through 152‘<samp>cvs63</samp>’. Therefore, this feature requires both 153‘<samp>org.gnu.gdb.power.htm.altivec</samp>’ and 154‘<samp>org.gnu.gdb.power.htm.fpu</samp>’. 155</p> 156<p>The ‘<samp>org.gnu.gdb.power.htm.ppr</samp>’ feature is optional. It should 157contain the 64-bit checkpointed register ‘<samp>cppr</samp>’. 158</p> 159<p>The ‘<samp>org.gnu.gdb.power.htm.dscr</samp>’ feature is optional. It should 160contain the 64-bit checkpointed register ‘<samp>cdscr</samp>’. 161</p> 162<p>The ‘<samp>org.gnu.gdb.power.htm.tar</samp>’ feature is optional. It should 163contain the 64-bit checkpointed register ‘<samp>ctar</samp>’. 164</p> 165 166<hr> 167<div class="header"> 168<p> 169Next: <a href="RISC_002dV-Features.html#RISC_002dV-Features" accesskey="n" rel="next">RISC-V Features</a>, Previous: <a href="OpenRISC-1000-Features.html#OpenRISC-1000-Features" accesskey="p" rel="previous">OpenRISC 1000 Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p> 170</div> 171 172 173 174</body> 175</html> 176