1*4882a593Smuzhiyun /*-*- linux-c -*- 2*4882a593Smuzhiyun * linux/drivers/video/i810_regs.h -- Intel 810/815 Register List 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net> 5*4882a593Smuzhiyun * All Rights Reserved 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 9*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive for 10*4882a593Smuzhiyun * more details. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Intel 810 Chipset Family PRM 15 3.1 16*4882a593Smuzhiyun * GC Register Memory Address Map 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Based on: 19*4882a593Smuzhiyun * Intel (R) 810 Chipset Family 20*4882a593Smuzhiyun * Programmer s Reference Manual 21*4882a593Smuzhiyun * November 1999 22*4882a593Smuzhiyun * Revision 1.0 23*4882a593Smuzhiyun * Order Number: 298026-001 R 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers 26*4882a593Smuzhiyun * are I/O mapped. 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #ifndef __I810_REGS_H__ 30*4882a593Smuzhiyun #define __I810_REGS_H__ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Instruction and Interrupt Control Registers (01000h 02FFFh) */ 33*4882a593Smuzhiyun #define FENCE 0x02000 34*4882a593Smuzhiyun #define PGTBL_CTL 0x02020 35*4882a593Smuzhiyun #define PGTBL_ER 0x02024 36*4882a593Smuzhiyun #define LRING 0x02030 37*4882a593Smuzhiyun #define IRING 0x02040 38*4882a593Smuzhiyun #define HWS_PGA 0x02080 39*4882a593Smuzhiyun #define IPEIR 0x02088 40*4882a593Smuzhiyun #define IPEHR 0x0208C 41*4882a593Smuzhiyun #define INSTDONE 0x02090 42*4882a593Smuzhiyun #define NOPID 0x02094 43*4882a593Smuzhiyun #define HWSTAM 0x02098 44*4882a593Smuzhiyun #define IER 0x020A0 45*4882a593Smuzhiyun #define IIR 0x020A4 46*4882a593Smuzhiyun #define IMR 0x020A8 47*4882a593Smuzhiyun #define ISR 0x020AC 48*4882a593Smuzhiyun #define EIR 0x020B0 49*4882a593Smuzhiyun #define EMR 0x020B4 50*4882a593Smuzhiyun #define ESR 0x020B8 51*4882a593Smuzhiyun #define INSTPM 0x020C0 52*4882a593Smuzhiyun #define INSTPS 0x020C4 53*4882a593Smuzhiyun #define BBP_PTR 0x020C8 54*4882a593Smuzhiyun #define ABB_SRT 0x020CC 55*4882a593Smuzhiyun #define ABB_END 0x020D0 56*4882a593Smuzhiyun #define DMA_FADD 0x020D4 57*4882a593Smuzhiyun #define FW_BLC 0x020D8 58*4882a593Smuzhiyun #define MEM_MODE 0x020DC 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Memory Control Registers (03000h 03FFFh) */ 61*4882a593Smuzhiyun #define DRT 0x03000 62*4882a593Smuzhiyun #define DRAMCL 0x03001 63*4882a593Smuzhiyun #define DRAMCH 0x03002 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Span Cursor Registers (04000h 04FFFh) */ 67*4882a593Smuzhiyun #define UI_SC_CTL 0x04008 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* I/O Control Registers (05000h 05FFFh) */ 70*4882a593Smuzhiyun #define HVSYNC 0x05000 71*4882a593Smuzhiyun #define GPIOA 0x05010 72*4882a593Smuzhiyun #define GPIOB 0x05014 73*4882a593Smuzhiyun #define GPIOC 0x0501C 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Clock Control and Power Management Registers (06000h 06FFFh) */ 76*4882a593Smuzhiyun #define DCLK_0D 0x06000 77*4882a593Smuzhiyun #define DCLK_1D 0x06004 78*4882a593Smuzhiyun #define DCLK_2D 0x06008 79*4882a593Smuzhiyun #define LCD_CLKD 0x0600C 80*4882a593Smuzhiyun #define DCLK_0DS 0x06010 81*4882a593Smuzhiyun #define PWR_CLKC 0x06014 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Graphics Translation Table Range Definition (10000h 1FFFFh) */ 84*4882a593Smuzhiyun #define GTT 0x10000 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Overlay Registers (30000h 03FFFFh) */ 87*4882a593Smuzhiyun #define OVOADDR 0x30000 88*4882a593Smuzhiyun #define DOVOSTA 0x30008 89*4882a593Smuzhiyun #define GAMMA 0x30010 90*4882a593Smuzhiyun #define OBUF_0Y 0x30100 91*4882a593Smuzhiyun #define OBUF_1Y 0x30104 92*4882a593Smuzhiyun #define OBUF_0U 0x30108 93*4882a593Smuzhiyun #define OBUF_0V 0x3010C 94*4882a593Smuzhiyun #define OBUF_1U 0x30110 95*4882a593Smuzhiyun #define OBUF_1V 0x30114 96*4882a593Smuzhiyun #define OVOSTRIDE 0x30118 97*4882a593Smuzhiyun #define YRGB_VPH 0x3011C 98*4882a593Smuzhiyun #define UV_VPH 0x30120 99*4882a593Smuzhiyun #define HORZ_PH 0x30124 100*4882a593Smuzhiyun #define INIT_PH 0x30128 101*4882a593Smuzhiyun #define DWINPOS 0x3012C 102*4882a593Smuzhiyun #define DWINSZ 0x30130 103*4882a593Smuzhiyun #define SWID 0x30134 104*4882a593Smuzhiyun #define SWIDQW 0x30138 105*4882a593Smuzhiyun #define SHEIGHT 0x3013F 106*4882a593Smuzhiyun #define YRGBSCALE 0x30140 107*4882a593Smuzhiyun #define UVSCALE 0x30144 108*4882a593Smuzhiyun #define OVOCLRCO 0x30148 109*4882a593Smuzhiyun #define OVOCLRC1 0x3014C 110*4882a593Smuzhiyun #define DCLRKV 0x30150 111*4882a593Smuzhiyun #define DLCRKM 0x30154 112*4882a593Smuzhiyun #define SCLRKVH 0x30158 113*4882a593Smuzhiyun #define SCLRKVL 0x3015C 114*4882a593Smuzhiyun #define SCLRKM 0x30160 115*4882a593Smuzhiyun #define OVOCONF 0x30164 116*4882a593Smuzhiyun #define OVOCMD 0x30168 117*4882a593Smuzhiyun #define AWINPOS 0x30170 118*4882a593Smuzhiyun #define AWINZ 0x30174 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* BLT Engine Status (40000h 4FFFFh) (Software Debug) */ 121*4882a593Smuzhiyun #define BR00 0x40000 122*4882a593Smuzhiyun #define BRO1 0x40004 123*4882a593Smuzhiyun #define BR02 0x40008 124*4882a593Smuzhiyun #define BR03 0x4000C 125*4882a593Smuzhiyun #define BR04 0x40010 126*4882a593Smuzhiyun #define BR05 0x40014 127*4882a593Smuzhiyun #define BR06 0x40018 128*4882a593Smuzhiyun #define BR07 0x4001C 129*4882a593Smuzhiyun #define BR08 0x40020 130*4882a593Smuzhiyun #define BR09 0x40024 131*4882a593Smuzhiyun #define BR10 0x40028 132*4882a593Smuzhiyun #define BR11 0x4002C 133*4882a593Smuzhiyun #define BR12 0x40030 134*4882a593Smuzhiyun #define BR13 0x40034 135*4882a593Smuzhiyun #define BR14 0x40038 136*4882a593Smuzhiyun #define BR15 0x4003C 137*4882a593Smuzhiyun #define BR16 0x40040 138*4882a593Smuzhiyun #define BR17 0x40044 139*4882a593Smuzhiyun #define BR18 0x40048 140*4882a593Smuzhiyun #define BR19 0x4004C 141*4882a593Smuzhiyun #define SSLADD 0x40074 142*4882a593Smuzhiyun #define DSLH 0x40078 143*4882a593Smuzhiyun #define DSLRADD 0x4007C 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */ 147*4882a593Smuzhiyun /* LCD/TV-Out */ 148*4882a593Smuzhiyun #define HTOTAL 0x60000 149*4882a593Smuzhiyun #define HBLANK 0x60004 150*4882a593Smuzhiyun #define HSYNC 0x60008 151*4882a593Smuzhiyun #define VTOTAL 0x6000C 152*4882a593Smuzhiyun #define VBLANK 0x60010 153*4882a593Smuzhiyun #define VSYNC 0x60014 154*4882a593Smuzhiyun #define LCDTV_C 0x60018 155*4882a593Smuzhiyun #define OVRACT 0x6001C 156*4882a593Smuzhiyun #define BCLRPAT 0x60020 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Display and Cursor Control Registers (70000h 7FFFFh) */ 159*4882a593Smuzhiyun #define DISP_SL 0x70000 160*4882a593Smuzhiyun #define DISP_SLC 0x70004 161*4882a593Smuzhiyun #define PIXCONF 0x70008 162*4882a593Smuzhiyun #define PIXCONF1 0x70009 163*4882a593Smuzhiyun #define BLTCNTL 0x7000C 164*4882a593Smuzhiyun #define SWF 0x70014 165*4882a593Smuzhiyun #define DPLYBASE 0x70020 166*4882a593Smuzhiyun #define DPLYSTAS 0x70024 167*4882a593Smuzhiyun #define CURCNTR 0x70080 168*4882a593Smuzhiyun #define CURBASE 0x70084 169*4882a593Smuzhiyun #define CURPOS 0x70088 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* VGA Registers */ 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun /* SMRAM Registers */ 175*4882a593Smuzhiyun #define SMRAM 0x10 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* Graphics Control Registers */ 178*4882a593Smuzhiyun #define GR_INDEX 0x3CE 179*4882a593Smuzhiyun #define GR_DATA 0x3CF 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define GR10 0x10 182*4882a593Smuzhiyun #define GR11 0x11 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* CRT Controller Registers */ 185*4882a593Smuzhiyun #define CR_INDEX_MDA 0x3B4 186*4882a593Smuzhiyun #define CR_INDEX_CGA 0x3D4 187*4882a593Smuzhiyun #define CR_DATA_MDA 0x3B5 188*4882a593Smuzhiyun #define CR_DATA_CGA 0x3D5 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define CR30 0x30 191*4882a593Smuzhiyun #define CR31 0x31 192*4882a593Smuzhiyun #define CR32 0x32 193*4882a593Smuzhiyun #define CR33 0x33 194*4882a593Smuzhiyun #define CR35 0x35 195*4882a593Smuzhiyun #define CR39 0x39 196*4882a593Smuzhiyun #define CR40 0x40 197*4882a593Smuzhiyun #define CR41 0x41 198*4882a593Smuzhiyun #define CR42 0x42 199*4882a593Smuzhiyun #define CR70 0x70 200*4882a593Smuzhiyun #define CR80 0x80 201*4882a593Smuzhiyun #define CR81 0x82 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Extended VGA Registers */ 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* General Control and Status Registers */ 206*4882a593Smuzhiyun #define ST00 0x3C2 207*4882a593Smuzhiyun #define ST01_MDA 0x3BA 208*4882a593Smuzhiyun #define ST01_CGA 0x3DA 209*4882a593Smuzhiyun #define FRC_READ 0x3CA 210*4882a593Smuzhiyun #define FRC_WRITE_MDA 0x3BA 211*4882a593Smuzhiyun #define FRC_WRITE_CGA 0x3DA 212*4882a593Smuzhiyun #define MSR_READ 0x3CC 213*4882a593Smuzhiyun #define MSR_WRITE 0x3C2 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* Sequencer Registers */ 216*4882a593Smuzhiyun #define SR_INDEX 0x3C4 217*4882a593Smuzhiyun #define SR_DATA 0x3C5 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun #define SR01 0x01 220*4882a593Smuzhiyun #define SR02 0x02 221*4882a593Smuzhiyun #define SR03 0x03 222*4882a593Smuzhiyun #define SR04 0x04 223*4882a593Smuzhiyun #define SR07 0x07 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* Graphics Controller Registers */ 226*4882a593Smuzhiyun #define GR00 0x00 227*4882a593Smuzhiyun #define GR01 0x01 228*4882a593Smuzhiyun #define GR02 0x02 229*4882a593Smuzhiyun #define GR03 0x03 230*4882a593Smuzhiyun #define GR04 0x04 231*4882a593Smuzhiyun #define GR05 0x05 232*4882a593Smuzhiyun #define GR06 0x06 233*4882a593Smuzhiyun #define GR07 0x07 234*4882a593Smuzhiyun #define GR08 0x08 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* Attribute Controller Registers */ 237*4882a593Smuzhiyun #define ATTR_WRITE 0x3C0 238*4882a593Smuzhiyun #define ATTR_READ 0x3C1 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* VGA Color Palette Registers */ 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun /* CLUT */ 243*4882a593Smuzhiyun #define CLUT_DATA 0x3C9 /* DACDATA */ 244*4882a593Smuzhiyun #define CLUT_INDEX_READ 0x3C7 /* DACRX */ 245*4882a593Smuzhiyun #define CLUT_INDEX_WRITE 0x3C8 /* DACWX */ 246*4882a593Smuzhiyun #define DACMASK 0x3C6 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun /* CRT Controller Registers */ 249*4882a593Smuzhiyun #define CR00 0x00 250*4882a593Smuzhiyun #define CR01 0x01 251*4882a593Smuzhiyun #define CR02 0x02 252*4882a593Smuzhiyun #define CR03 0x03 253*4882a593Smuzhiyun #define CR04 0x04 254*4882a593Smuzhiyun #define CR05 0x05 255*4882a593Smuzhiyun #define CR06 0x06 256*4882a593Smuzhiyun #define CR07 0x07 257*4882a593Smuzhiyun #define CR08 0x08 258*4882a593Smuzhiyun #define CR09 0x09 259*4882a593Smuzhiyun #define CR0A 0x0A 260*4882a593Smuzhiyun #define CR0B 0x0B 261*4882a593Smuzhiyun #define CR0C 0x0C 262*4882a593Smuzhiyun #define CR0D 0x0D 263*4882a593Smuzhiyun #define CR0E 0x0E 264*4882a593Smuzhiyun #define CR0F 0x0F 265*4882a593Smuzhiyun #define CR10 0x10 266*4882a593Smuzhiyun #define CR11 0x11 267*4882a593Smuzhiyun #define CR12 0x12 268*4882a593Smuzhiyun #define CR13 0x13 269*4882a593Smuzhiyun #define CR14 0x14 270*4882a593Smuzhiyun #define CR15 0x15 271*4882a593Smuzhiyun #define CR16 0x16 272*4882a593Smuzhiyun #define CR17 0x17 273*4882a593Smuzhiyun #define CR18 0x18 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #endif /* __I810_REGS_H__ */ 276