1 /** @file mlan_sdio.h 2 * 3 * @brief This file contains definitions for SDIO interface. 4 * driver. 5 * 6 * 7 * Copyright 2008-2021 NXP 8 * 9 * This software file (the File) is distributed by NXP 10 * under the terms of the GNU General Public License Version 2, June 1991 11 * (the License). You may use, redistribute and/or modify the File in 12 * accordance with the terms and conditions of the License, a copy of which 13 * is available by writing to the Free Software Foundation, Inc., 14 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 15 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 16 * 17 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 19 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 20 * this warranty disclaimer. 21 * 22 */ 23 /**************************************************** 24 Change log: 25 ****************************************************/ 26 27 #ifndef _MLAN_SDIO_H 28 #define _MLAN_SDIO_H 29 30 /** Block mode */ 31 #ifndef BLOCK_MODE 32 #define BLOCK_MODE 1 33 #endif 34 35 /** Fixed address mode */ 36 #ifndef FIXED_ADDRESS 37 #define FIXED_ADDRESS 0 38 #endif 39 40 /* Host Control Registers */ 41 /** Host Control Registers : Host to Card Event */ 42 #define HOST_TO_CARD_EVENT_REG 0x00 43 /** Host Control Registers : Host terminates Command 53 */ 44 #define HOST_TERM_CMD53 (0x1U << 2) 45 /** Host Control Registers : Host without Command 53 finish host */ 46 #define HOST_WO_CMD53_FINISH_HOST (0x1U << 2) 47 /** Host Control Registers : Host power up */ 48 #define HOST_POWER_UP (0x1U << 1) 49 /** Host Control Registers : Host power down */ 50 #define HOST_POWER_DOWN (0x1U << 0) 51 52 /** Host Control Registers : Upload host interrupt RSR */ 53 #define UP_LD_HOST_INT_RSR (0x1U) 54 #define HOST_INT_RSR_MASK 0xFF 55 56 /** Host Control Registers : Upload command port host interrupt status */ 57 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) 58 /** Host Control Registers : Download command port host interrupt status */ 59 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) 60 61 /** Host Control Registers : Upload host interrupt mask */ 62 #define UP_LD_HOST_INT_MASK (0x1U) 63 /** Host Control Registers : Download host interrupt mask */ 64 #define DN_LD_HOST_INT_MASK (0x2U) 65 /** Host Control Registers : Cmd port upload interrupt mask */ 66 #define CMD_PORT_UPLD_INT_MASK (0x1U << 6) 67 /** Host Control Registers : Cmd port download interrupt mask */ 68 #define CMD_PORT_DNLD_INT_MASK (0x1U << 7) 69 /** Enable Host interrupt mask */ 70 #define HIM_ENABLE \ 71 (UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | CMD_PORT_UPLD_INT_MASK | \ 72 CMD_PORT_DNLD_INT_MASK) 73 /** Disable Host interrupt mask */ 74 #define HIM_DISABLE 0xff 75 76 /** Host Control Registers : Upload host interrupt status */ 77 #define UP_LD_HOST_INT_STATUS (0x1U) 78 /** Host Control Registers : Download host interrupt status */ 79 #define DN_LD_HOST_INT_STATUS (0x2U) 80 81 /** Host Control Registers : Download CRC error */ 82 #define DN_LD_CRC_ERR (0x1U << 2) 83 /** Host Control Registers : Upload restart */ 84 #define UP_LD_RESTART (0x1U << 1) 85 /** Host Control Registers : Download restart */ 86 #define DN_LD_RESTART (0x1U << 0) 87 88 /** Card Control Registers : Command port upload ready */ 89 #define UP_LD_CP_RDY (0x1U << 6) 90 /** Card Control Registers : Command port download ready */ 91 #define DN_LD_CP_RDY (0x1U << 7) 92 /** Card Control Registers : Card I/O ready */ 93 #define CARD_IO_READY (0x1U << 3) 94 /** Card Control Registers : CIS card ready */ 95 #define CIS_CARD_RDY (0x1U << 2) 96 /** Card Control Registers : Upload card ready */ 97 #define UP_LD_CARD_RDY (0x1U << 1) 98 /** Card Control Registers : Download card ready */ 99 #define DN_LD_CARD_RDY (0x1U << 0) 100 101 /** Card Control Registers : Host power interrupt mask */ 102 #define HOST_POWER_INT_MASK (0x1U << 3) 103 /** Card Control Registers : Abort card interrupt mask */ 104 #define ABORT_CARD_INT_MASK (0x1U << 2) 105 /** Card Control Registers : Upload card interrupt mask */ 106 #define UP_LD_CARD_INT_MASK (0x1U << 1) 107 /** Card Control Registers : Download card interrupt mask */ 108 #define DN_LD_CARD_INT_MASK (0x1U << 0) 109 110 /** Card Control Registers : Power up interrupt */ 111 #define POWER_UP_INT (0x1U << 4) 112 /** Card Control Registers : Power down interrupt */ 113 #define POWER_DOWN_INT (0x1U << 3) 114 115 /** Card Control Registers : Power up RSR */ 116 #define POWER_UP_RSR (0x1U << 4) 117 /** Card Control Registers : Power down RSR */ 118 #define POWER_DOWN_RSR (0x1U << 3) 119 120 /** Card Control Registers : SD test BUS 0 */ 121 #define SD_TESTBUS0 (0x1U) 122 /** Card Control Registers : SD test BUS 1 */ 123 #define SD_TESTBUS1 (0x1U) 124 /** Card Control Registers : SD test BUS 2 */ 125 #define SD_TESTBUS2 (0x1U) 126 /** Card Control Registers : SD test BUS 3 */ 127 #define SD_TESTBUS3 (0x1U) 128 129 /** Port for registers */ 130 #define REG_PORT 0 131 /** Port for memory */ 132 #define MEM_PORT 0x10000 133 /** Ctrl port */ 134 #define CTRL_PORT 0 135 /** Ctrl port mask */ 136 #define CTRL_PORT_MASK 0x0001 137 /** Card Control Registers : cmd53 new mode */ 138 #define CMD53_NEW_MODE (0x1U << 0) 139 /** Card Control Registers : cmd53 tx len format 1 (0x10) */ 140 #define CMD53_TX_LEN_FORMAT_1 (0x1U << 4) 141 /** Card Control Registers : cmd53 tx len format 2 (0x20)*/ 142 #define CMD53_TX_LEN_FORMAT_2 (0x1U << 5) 143 /** Card Control Registers : cmd53 rx len format 1 (0x40) */ 144 #define CMD53_RX_LEN_FORMAT_1 (0x1U << 6) 145 /** Card Control Registers : cmd53 rx len format 2 (0x80)*/ 146 #define CMD53_RX_LEN_FORMAT_2 (0x1U << 7) 147 148 #define CMD_PORT_RD_LEN_EN (0x1U << 2) 149 /* Card Control Registers : cmd port auto enable */ 150 #define CMD_PORT_AUTO_EN (0x1U << 0) 151 152 /* Command port */ 153 #define CMD_PORT_SLCT 0x8000 154 155 /** Misc. Config Register : Auto Re-enable interrupts */ 156 #define AUTO_RE_ENABLE_INT MBIT(4) 157 158 /** Enable GPIO-1 as a duplicated signal of interrupt as appear of SDIO_DAT1*/ 159 #define ENABLE_GPIO_1_INT_MODE 0x88 160 /** Scratch reg 3 2 : Configure GPIO-1 INT*/ 161 #define SCRATCH_REG_32 0xEE 162 163 /** Event header Len*/ 164 #define MLAN_EVENT_HEADER_LEN 8 165 166 /** SDIO byte mode size */ 167 #define MAX_BYTE_MODE_SIZE 512 168 169 /** The base address for packet with multiple ports aggregation */ 170 #define SDIO_MPA_ADDR_BASE 0x1000 171 172 /** SDIO Tx aggregation in progress ? */ 173 #define MP_TX_AGGR_IN_PROGRESS(a) (a->pcard_sd->mpa_tx.pkt_cnt > 0) 174 175 /** SDIO Tx aggregation buffer room for next packet ? */ 176 #define MP_TX_AGGR_BUF_HAS_ROOM(a, mbuf, len) \ 177 (((a->pcard_sd->mpa_tx.buf_len) + len) <= \ 178 (a->pcard_sd->mpa_tx.buf_size)) 179 180 /** Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ 181 #define MP_TX_AGGR_BUF_PUT(a, mbuf, port) \ 182 do { \ 183 pmadapter->callbacks.moal_memmove( \ 184 a->pmoal_handle, \ 185 &a->pcard_sd->mpa_tx.buf[a->pcard_sd->mpa_tx.buf_len], \ 186 mbuf->pbuf + mbuf->data_offset, mbuf->data_len); \ 187 a->pcard_sd->mpa_tx.buf_len += mbuf->data_len; \ 188 a->pcard_sd->mpa_tx.mp_wr_info[a->pcard_sd->mpa_tx.pkt_cnt] = \ 189 *(t_u16 *)(mbuf->pbuf + mbuf->data_offset); \ 190 if (!a->pcard_sd->mpa_tx.pkt_cnt) { \ 191 a->pcard_sd->mpa_tx.start_port = port; \ 192 } \ 193 a->pcard_sd->mpa_tx.ports |= (1 << port); \ 194 a->pcard_sd->mpa_tx.pkt_cnt++; \ 195 } while (0) 196 197 #define MP_TX_AGGR_BUF_PUT_NONEWMODE(a, mbuf, port) \ 198 do { \ 199 pmadapter->callbacks.moal_memmove( \ 200 a->pmoal_handle, \ 201 &a->pcard_sd->mpa_tx.buf[a->pcard_sd->mpa_tx.buf_len], \ 202 mbuf->pbuf + mbuf->data_offset, mbuf->data_len); \ 203 a->pcard_sd->mpa_tx.buf_len += mbuf->data_len; \ 204 a->pcard_sd->mpa_tx.mp_wr_info[a->pcard_sd->mpa_tx.pkt_cnt] = \ 205 *(t_u16 *)(mbuf->pbuf + mbuf->data_offset); \ 206 if (!a->pcard_sd->mpa_tx.pkt_cnt) { \ 207 a->pcard_sd->mpa_tx.start_port = port; \ 208 } \ 209 if (a->pcard_sd->mpa_tx.start_port <= port) { \ 210 a->pcard_sd->mpa_tx.ports |= \ 211 (1 << (a->pcard_sd->mpa_tx.pkt_cnt)); \ 212 } else { \ 213 a->pcard_sd->mpa_tx.ports |= \ 214 (1 << (a->pcard_sd->mpa_tx.pkt_cnt + 1 + \ 215 (a->pcard_sd->max_ports - \ 216 a->pcard_sd->mp_end_port))); \ 217 } \ 218 a->pcard_sd->mpa_tx.pkt_cnt++; \ 219 } while (0) 220 #define MP_TX_AGGR_BUF_PUT_SG(a, mbuf, port) \ 221 do { \ 222 a->pcard_sd->mpa_tx.buf_len += mbuf->data_len; \ 223 a->pcard_sd->mpa_tx.mp_wr_info[a->pcard_sd->mpa_tx.pkt_cnt] = \ 224 *(t_u16 *)(mbuf->pbuf + mbuf->data_offset); \ 225 a->pcard_sd->mpa_tx.mbuf_arr[a->pcard_sd->mpa_tx.pkt_cnt] = \ 226 mbuf; \ 227 if (!a->pcard_sd->mpa_tx.pkt_cnt) { \ 228 a->pcard_sd->mpa_tx.start_port = port; \ 229 } \ 230 a->pcard_sd->mpa_tx.ports |= (1 << port); \ 231 a->pcard_sd->mpa_tx.pkt_cnt++; \ 232 } while (0) 233 #define MP_TX_AGGR_BUF_PUT_SG_NONEWMODE(a, mbuf, port) \ 234 do { \ 235 a->pcard_sd->mpa_tx.buf_len += mbuf->data_len; \ 236 a->pcard_sd->mpa_tx.mp_wr_info[a->pcard_sd->mpa_tx.pkt_cnt] = \ 237 *(t_u16 *)(mbuf->pbuf + mbuf->data_offset); \ 238 a->pcard_sd->mpa_tx.mbuf_arr[a->pcard_sd->mpa_tx.pkt_cnt] = \ 239 mbuf; \ 240 if (!a->pcard_sd->mpa_tx.pkt_cnt) { \ 241 a->pcard_sd->mpa_tx.start_port = port; \ 242 } \ 243 if (a->pcard_sd->mpa_tx.start_port <= port) { \ 244 a->pcard_sd->mpa_tx.ports |= \ 245 (1 << (a->pcard_sd->mpa_tx.pkt_cnt)); \ 246 } else { \ 247 a->pcard_sd->mpa_tx.ports |= \ 248 (1 << (a->pcard_sd->mpa_tx.pkt_cnt + 1 + \ 249 (a->pcard_sd->max_ports - \ 250 a->pcard_sd->mp_end_port))); \ 251 } \ 252 a->pcard_sd->mpa_tx.pkt_cnt++; \ 253 } while (0) 254 255 /** SDIO Tx aggregation limit ? */ 256 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \ 257 ((a->pcard_sd->mpa_tx.pkt_cnt) == (a->pcard_sd->mpa_tx.pkt_aggr_limit)) 258 259 #define MP_TX_AGGR_PORT_LIMIT_REACHED(a) \ 260 ((a->pcard_sd->curr_wr_port < a->pcard_sd->mpa_tx.start_port) && \ 261 (((a->pcard_sd->max_ports - a->pcard_sd->mpa_tx.start_port) + \ 262 a->pcard_sd->curr_wr_port) >= a->pcard_sd->mp_aggr_pkt_limit)) 263 264 /** Reset SDIO Tx aggregation buffer parameters */ 265 #define MP_TX_AGGR_BUF_RESET(a) \ 266 do { \ 267 memset(a, a->pcard_sd->mpa_tx.mp_wr_info, 0, \ 268 sizeof(a->pcard_sd->mpa_tx.mp_wr_info)); \ 269 a->pcard_sd->mpa_tx.pkt_cnt = 0; \ 270 a->pcard_sd->mpa_tx.buf_len = 0; \ 271 a->pcard_sd->mpa_tx.ports = 0; \ 272 a->pcard_sd->mpa_tx.start_port = 0; \ 273 } while (0) 274 275 /** SDIO Rx aggregation limit ? */ 276 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \ 277 (a->pcard_sd->mpa_rx.pkt_cnt == a->pcard_sd->mpa_rx.pkt_aggr_limit) 278 279 /** SDIO Rx aggregation port limit ? */ 280 /** this is for test only, because port 0 is reserved for control port */ 281 /* #define MP_RX_AGGR_PORT_LIMIT_REACHED(a) (a->curr_rd_port == 1) */ 282 283 /* receive packets aggregated up to a half of mp_end_port */ 284 /* note: hw rx wraps round only after port (MAX_PORT-1) */ 285 #define MP_RX_AGGR_PORT_LIMIT_REACHED(a) \ 286 (((a->pcard_sd->curr_rd_port < a->pcard_sd->mpa_rx.start_port) && \ 287 (((a->pcard_sd->max_ports - a->pcard_sd->mpa_rx.start_port) + \ 288 a->pcard_sd->curr_rd_port) >= (a->pcard_sd->mp_end_port >> 1))) || \ 289 ((a->pcard_sd->curr_rd_port - a->pcard_sd->mpa_rx.start_port) >= \ 290 (a->pcard_sd->mp_end_port >> 1))) 291 292 #define MP_RX_AGGR_PORT_LIMIT_REACHED_NONEWMODE(a) \ 293 ((a->pcard_sd->curr_rd_port < a->pcard_sd->mpa_rx.start_port) && \ 294 (((a->pcard_sd->max_ports - a->pcard_sd->mpa_rx.start_port) + \ 295 a->pcard_sd->curr_rd_port) >= a->pcard_sd->mp_aggr_pkt_limit)) 296 297 /** SDIO Rx aggregation in progress ? */ 298 #define MP_RX_AGGR_IN_PROGRESS(a) (a->pcard_sd->mpa_rx.pkt_cnt > 0) 299 300 /** SDIO Rx aggregation buffer room for next packet ? */ 301 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \ 302 ((a->pcard_sd->mpa_rx.buf_len + rx_len) <= a->pcard_sd->mpa_rx.buf_size) 303 304 /** Prepare to copy current packet from card to SDIO Rx aggregation buffer */ 305 #define MP_RX_AGGR_SETUP(a, mbuf, port, rx_len) \ 306 do { \ 307 a->pcard_sd->mpa_rx.buf_len += rx_len; \ 308 if (!a->pcard_sd->mpa_rx.pkt_cnt) { \ 309 a->pcard_sd->mpa_rx.start_port = port; \ 310 } \ 311 a->pcard_sd->mpa_rx.ports |= (1 << port); \ 312 a->pcard_sd->mpa_rx.mbuf_arr[a->pcard_sd->mpa_rx.pkt_cnt] = \ 313 mbuf; \ 314 a->pcard_sd->mpa_rx.len_arr[a->pcard_sd->mpa_rx.pkt_cnt] = \ 315 rx_len; \ 316 a->pcard_sd->mpa_rx.pkt_cnt++; \ 317 } while (0) 318 319 #define MP_RX_AGGR_SETUP_NONEWMODE(a, mbuf, port, rx_len) \ 320 do { \ 321 a->pcard_sd->mpa_rx.buf_len += rx_len; \ 322 if (!a->pcard_sd->mpa_rx.pkt_cnt) { \ 323 a->pcard_sd->mpa_rx.start_port = port; \ 324 } \ 325 if (a->pcard_sd->mpa_rx.start_port <= port) { \ 326 a->pcard_sd->mpa_rx.ports |= \ 327 (1 << (a->pcard_sd->mpa_rx.pkt_cnt)); \ 328 } else { \ 329 a->pcard_sd->mpa_rx.ports |= \ 330 (1 << (a->pcard_sd->mpa_rx.pkt_cnt + 1)); \ 331 } \ 332 a->pcard_sd->mpa_rx.mbuf_arr[a->pcard_sd->mpa_rx.pkt_cnt] = \ 333 mbuf; \ 334 a->pcard_sd->mpa_rx.len_arr[a->pcard_sd->mpa_rx.pkt_cnt] = \ 335 rx_len; \ 336 a->pcard_sd->mpa_rx.pkt_cnt++; \ 337 } while (0); 338 339 /** Reset SDIO Rx aggregation buffer parameters */ 340 #define MP_RX_AGGR_BUF_RESET(a) \ 341 do { \ 342 a->pcard_sd->mpa_rx.pkt_cnt = 0; \ 343 a->pcard_sd->mpa_rx.buf_len = 0; \ 344 a->pcard_sd->mpa_rx.ports = 0; \ 345 a->pcard_sd->mpa_rx.start_port = 0; \ 346 } while (0) 347 348 /** aggr buf size 32k */ 349 #define SDIO_MP_AGGR_BUF_SIZE_32K (32768) 350 /** max aggr buf size 64k-256 */ 351 #define SDIO_MP_AGGR_BUF_SIZE_MAX (65280) 352 353 extern mlan_adapter_operations mlan_sdio_ops; 354 355 /** Probe and initialization function */ 356 mlan_status wlan_sdio_probe(pmlan_adapter pmadapter); 357 mlan_status wlan_get_sdio_device(pmlan_adapter pmadapter); 358 359 mlan_status wlan_send_mp_aggr_buf(mlan_adapter *pmadapter); 360 361 mlan_status wlan_re_alloc_sdio_rx_mpa_buffer(mlan_adapter *pmadapter); 362 363 void wlan_decode_spa_buffer(mlan_adapter *pmadapter, t_u8 *buf, t_u32 len); 364 t_void wlan_sdio_deaggr_rx_pkt(pmlan_adapter pmadapter, mlan_buffer *pmbuf); 365 /** Transfer data to card */ 366 mlan_status wlan_sdio_host_to_card(mlan_adapter *pmadapter, t_u8 type, 367 mlan_buffer *mbuf, mlan_tx_param *tx_param); 368 mlan_status wlan_set_sdio_gpio_int(pmlan_private priv); 369 mlan_status wlan_cmd_sdio_gpio_int(pmlan_private pmpriv, 370 HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, 371 t_void *pdata_buf); 372 mlan_status wlan_reset_fw(pmlan_adapter pmadapter); 373 374 #endif /* _MLAN_SDIO_H */ 375