1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * NOTE: This header file is not meant to be included directly. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* This header file contains assembly-language definitions (assembly 8*4882a593Smuzhiyun macros, etc.) for this specific Xtensa processor's TIE extensions 9*4882a593Smuzhiyun and options. It is customized to this Xtensa processor configuration. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun Copyright (c) 1999-2015 Cadence Design Systems Inc. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun Permission is hereby granted, free of charge, to any person obtaining 14*4882a593Smuzhiyun a copy of this software and associated documentation files (the 15*4882a593Smuzhiyun "Software"), to deal in the Software without restriction, including 16*4882a593Smuzhiyun without limitation the rights to use, copy, modify, merge, publish, 17*4882a593Smuzhiyun distribute, sublicense, and/or sell copies of the Software, and to 18*4882a593Smuzhiyun permit persons to whom the Software is furnished to do so, subject to 19*4882a593Smuzhiyun the following conditions: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun The above copyright notice and this permission notice shall be included 22*4882a593Smuzhiyun in all copies or substantial portions of the Software. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25*4882a593Smuzhiyun EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26*4882a593Smuzhiyun MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27*4882a593Smuzhiyun IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28*4882a593Smuzhiyun CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29*4882a593Smuzhiyun TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30*4882a593Smuzhiyun SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef _XTENSA_CORE_TIE_ASM_H 33*4882a593Smuzhiyun #define _XTENSA_CORE_TIE_ASM_H 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Selection parameter values for save-area save/restore macros: */ 36*4882a593Smuzhiyun /* Option vs. TIE: */ 37*4882a593Smuzhiyun #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 38*4882a593Smuzhiyun #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 39*4882a593Smuzhiyun #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 40*4882a593Smuzhiyun /* Whether used automatically by compiler: */ 41*4882a593Smuzhiyun #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 42*4882a593Smuzhiyun #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 43*4882a593Smuzhiyun #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 44*4882a593Smuzhiyun /* ABI handling across function calls: */ 45*4882a593Smuzhiyun #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 46*4882a593Smuzhiyun #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 47*4882a593Smuzhiyun #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 48*4882a593Smuzhiyun #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 49*4882a593Smuzhiyun /* Misc */ 50*4882a593Smuzhiyun #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 51*4882a593Smuzhiyun #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 52*4882a593Smuzhiyun | ((ccuse) & XTHAL_SAS_ANYCC) \ 53*4882a593Smuzhiyun | ((abi) & XTHAL_SAS_ANYABI) ) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Macro to store all non-coprocessor (extra) custom TIE and optional state 58*4882a593Smuzhiyun * (not including zero-overhead loop registers). 59*4882a593Smuzhiyun * Required parameters: 60*4882a593Smuzhiyun * ptr Save area pointer address register (clobbered) 61*4882a593Smuzhiyun * (register must contain a 4 byte aligned address). 62*4882a593Smuzhiyun * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 63*4882a593Smuzhiyun * registers are clobbered, the remaining are unused). 64*4882a593Smuzhiyun * Optional parameters: 65*4882a593Smuzhiyun * continue If macro invoked as part of a larger store sequence, set to 1 66*4882a593Smuzhiyun * if this is not the first in the sequence. Defaults to 0. 67*4882a593Smuzhiyun * ofs Offset from start of larger sequence (from value of first ptr 68*4882a593Smuzhiyun * in sequence) at which to store. Defaults to next available space 69*4882a593Smuzhiyun * (or 0 if <continue> is 0). 70*4882a593Smuzhiyun * select Select what category(ies) of registers to store, as a bitmask 71*4882a593Smuzhiyun * (see XTHAL_SAS_xxx constants). Defaults to all registers. 72*4882a593Smuzhiyun * alloc Select what category(ies) of registers to allocate; if any 73*4882a593Smuzhiyun * category is selected here that is not in <select>, space for 74*4882a593Smuzhiyun * the corresponding registers is skipped without doing any store. 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 77*4882a593Smuzhiyun xchal_sa_start \continue, \ofs 78*4882a593Smuzhiyun // Optional caller-saved registers used by default by the compiler: 79*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 80*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1016, 4, 4 81*4882a593Smuzhiyun rsr.ACCLO \at1 // MAC16 option 82*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_+0 83*4882a593Smuzhiyun rsr.ACCHI \at1 // MAC16 option 84*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_+4 85*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 86*4882a593Smuzhiyun .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 87*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1016, 4, 4 88*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 89*4882a593Smuzhiyun .endif 90*4882a593Smuzhiyun // Optional caller-saved registers not used by default by the compiler: 91*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 92*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1004, 4, 4 93*4882a593Smuzhiyun rsr.SCOMPARE1 \at1 // conditional store option 94*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_+0 95*4882a593Smuzhiyun rsr.M0 \at1 // MAC16 option 96*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_+4 97*4882a593Smuzhiyun rsr.M1 \at1 // MAC16 option 98*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_+8 99*4882a593Smuzhiyun rsr.M2 \at1 // MAC16 option 100*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_+12 101*4882a593Smuzhiyun rsr.M3 \at1 // MAC16 option 102*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_+16 103*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 104*4882a593Smuzhiyun .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 105*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1004, 4, 4 106*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 107*4882a593Smuzhiyun .endif 108*4882a593Smuzhiyun .endm // xchal_ncp_store 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * Macro to load all non-coprocessor (extra) custom TIE and optional state 112*4882a593Smuzhiyun * (not including zero-overhead loop registers). 113*4882a593Smuzhiyun * Required parameters: 114*4882a593Smuzhiyun * ptr Save area pointer address register (clobbered) 115*4882a593Smuzhiyun * (register must contain a 4 byte aligned address). 116*4882a593Smuzhiyun * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 117*4882a593Smuzhiyun * registers are clobbered, the remaining are unused). 118*4882a593Smuzhiyun * Optional parameters: 119*4882a593Smuzhiyun * continue If macro invoked as part of a larger load sequence, set to 1 120*4882a593Smuzhiyun * if this is not the first in the sequence. Defaults to 0. 121*4882a593Smuzhiyun * ofs Offset from start of larger sequence (from value of first ptr 122*4882a593Smuzhiyun * in sequence) at which to load. Defaults to next available space 123*4882a593Smuzhiyun * (or 0 if <continue> is 0). 124*4882a593Smuzhiyun * select Select what category(ies) of registers to load, as a bitmask 125*4882a593Smuzhiyun * (see XTHAL_SAS_xxx constants). Defaults to all registers. 126*4882a593Smuzhiyun * alloc Select what category(ies) of registers to allocate; if any 127*4882a593Smuzhiyun * category is selected here that is not in <select>, space for 128*4882a593Smuzhiyun * the corresponding registers is skipped without doing any load. 129*4882a593Smuzhiyun */ 130*4882a593Smuzhiyun .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 131*4882a593Smuzhiyun xchal_sa_start \continue, \ofs 132*4882a593Smuzhiyun // Optional caller-saved registers used by default by the compiler: 133*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 134*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1016, 4, 4 135*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_+0 136*4882a593Smuzhiyun wsr.ACCLO \at1 // MAC16 option 137*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_+4 138*4882a593Smuzhiyun wsr.ACCHI \at1 // MAC16 option 139*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 140*4882a593Smuzhiyun .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 141*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1016, 4, 4 142*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 143*4882a593Smuzhiyun .endif 144*4882a593Smuzhiyun // Optional caller-saved registers not used by default by the compiler: 145*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 146*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1004, 4, 4 147*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_+0 148*4882a593Smuzhiyun wsr.SCOMPARE1 \at1 // conditional store option 149*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_+4 150*4882a593Smuzhiyun wsr.M0 \at1 // MAC16 option 151*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_+8 152*4882a593Smuzhiyun wsr.M1 \at1 // MAC16 option 153*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_+12 154*4882a593Smuzhiyun wsr.M2 \at1 // MAC16 option 155*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_+16 156*4882a593Smuzhiyun wsr.M3 \at1 // MAC16 option 157*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 158*4882a593Smuzhiyun .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 159*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1004, 4, 4 160*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 161*4882a593Smuzhiyun .endif 162*4882a593Smuzhiyun .endm // xchal_ncp_load 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define XCHAL_NCP_NUM_ATMPS 1 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define XCHAL_SA_NUM_ATMPS 1 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #endif /*_XTENSA_CORE_TIE_ASM_H*/ 170*4882a593Smuzhiyun 171