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/OK3568_Linux_fs/kernel/arch/parisc/include/asm/
H A Dasmregs.h11 rp: .reg %r2
12 arg3: .reg %r23
13 arg2: .reg %r24
14 arg1: .reg %r25
15 arg0: .reg %r26
16 dp: .reg %r27
17 ret0: .reg %r28
18 ret1: .reg %r29
19 sl: .reg %r29
20 sp: .reg %r30
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dasm-eva.h19 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument
20 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument
21 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument
22 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument
23 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument
24 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument
25 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument
26 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument
27 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument
28 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Danalogix_dp_reg.c37 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) in analogix_dp_write() argument
40 writel(val, dp->reg_base + reg); in analogix_dp_write()
41 writel(val, dp->reg_base + reg); in analogix_dp_write()
44 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) in analogix_dp_read() argument
46 readl(dp->reg_base + reg); in analogix_dp_read()
48 return readl(dp->reg_base + reg); in analogix_dp_read()
53 u32 reg; in analogix_dp_enable_video_mute() local
56 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
57 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
58 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); in analogix_dp_enable_video_mute()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c22 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) in analogix_dp_write() argument
26 writel(val, dp->reg_base + reg); in analogix_dp_write()
29 writel(val, dp->reg_base + reg); in analogix_dp_write()
32 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) in analogix_dp_read() argument
35 readl(dp->reg_base + reg); in analogix_dp_read()
37 return readl(dp->reg_base + reg); in analogix_dp_read()
42 u32 reg; in analogix_dp_enable_video_mute() local
45 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
46 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
47 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); in analogix_dp_enable_video_mute()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/
H A Darm32_macros.S8 .macro read_midr reg argument
9 mrc p15, 0, \reg, c0, c0, 0
12 .macro read_ctr reg argument
13 mrc p15, 0, \reg, c0, c0, 1
16 .macro read_mpidr reg argument
17 mrc p15, 0, \reg, c0, c0, 5
20 .macro read_sctlr reg argument
21 mrc p15, 0, \reg, c1, c0, 0
24 .macro write_sctlr reg argument
25 mcr p15, 0, \reg, c1, c0, 0
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk628/
H A Drk628_hdmirx.c27 #define REG(x) ((x) + 0x30000) macro
28 #define HDMI_RX_HDMI_SETUP_CTRL REG(0x0000)
31 #define HDMI_RX_HDMI_OVR_CTRL REG(0x0004)
32 #define HDMI_RX_HDMI_TIMER_CTRL REG(0x0008)
33 #define HDMI_RX_HDMI_RES_OVR REG(0x0010)
34 #define HDMI_RX_HDMI_RES_STS REG(0x0014)
35 #define HDMI_RX_HDMI_PLL_CTRL REG(0x0018)
36 #define HDMI_RX_HDMI_PLL_FRQSET1 REG(0x001c)
37 #define HDMI_RX_HDMI_PLL_FRQSET2 REG(0x0020)
38 #define HDMI_RX_HDMI_PLL_PAR1 REG(0x0024)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h36 * REG ==> macro to location of register offset
37 * eg. aud110->regs->reg
40 dm_read_reg(CTX, REG(reg_name))
43 dm_write_reg(CTX, REG(reg_name), value)
56 REG(reg_name), \
67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
68 REG_SET_N(reg, 2, init_value, \
69 FN(reg, f1), v1,\
70 FN(reg, f2), v2)
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.c25 unsigned int reg; in exynos_dp_enable_video_input() local
27 reg = readl(&dp_regs->video_ctl1); in exynos_dp_enable_video_input()
28 reg &= ~VIDEO_EN_MASK; in exynos_dp_enable_video_input()
32 reg |= VIDEO_EN_MASK; in exynos_dp_enable_video_input()
34 writel(reg, &dp_regs->video_ctl1); in exynos_dp_enable_video_input()
42 unsigned int reg; in exynos_dp_enable_video_bist() local
44 reg = readl(&dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
45 reg &= ~VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
49 reg |= VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
51 writel(reg, &dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
[all …]
H A Dexynos_mipi_dsi_lowlevel.c21 unsigned int reg; in exynos_mipi_dsi_func_reset() local
26 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
28 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
30 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
35 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
40 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
43 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
45 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
52 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/powerpc/include/
H A Dvmx_asm.h9 #define PUSH_VMX(pos,reg) \ argument
10 li reg,pos; \
11 stvx v20,reg,%r1; \
12 addi reg,reg,16; \
13 stvx v21,reg,%r1; \
14 addi reg,reg,16; \
15 stvx v22,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v23,reg,%r1; \
18 addi reg,reg,16; \
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/s5p-jpeg/
H A Djpeg-hw-s5p.c19 unsigned long reg; in s5p_jpeg_reset() local
22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
24 while (reg != 0) { in s5p_jpeg_reset()
26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
37 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local
45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
46 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode()
47 reg |= m; in s5p_jpeg_input_raw_mode()
48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
53 unsigned long reg, m; in s5p_jpeg_proc_mode() local
[all …]
H A Djpeg-hw-exynos4.c18 unsigned int reg; in exynos4_jpeg_sw_reset() local
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
34 unsigned int reg; in exynos4_jpeg_set_enc_dec_mode() local
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
[all …]
H A Djpeg-hw-exynos3250.c20 u32 reg = 1; in exynos3250_jpeg_reset() local
25 while (reg != 0 && --count > 0) { in exynos3250_jpeg_reset()
28 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
31 reg = 0; in exynos3250_jpeg_reset()
34 while (reg != 1 && --count > 0) { in exynos3250_jpeg_reset()
38 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
62 u32 reg; in exynos3250_jpeg_clk_set() local
64 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set()
66 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
71 u32 reg; in exynos3250_jpeg_input_raw_fmt() local
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/
H A Dqla_dbg.c108 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local
121 wrt_reg_word(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram()
122 wrt_reg_word(&reg->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram()
123 wrt_reg_word(&reg->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram()
125 wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
126 wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
127 wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
128 wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
130 wrt_reg_word(&reg->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram()
131 wrt_reg_word(&reg->mailbox5, LSW(dwords)); in qla27xx_dump_mpi_ram()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/cec/platform/s5p/
H A Dexynos_hdmi_cecctrl.c26 unsigned int reg; in s5p_cec_set_divider() local
30 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, &reg)) { in s5p_cec_set_divider()
35 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider()
37 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider()
44 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider()
45 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider()
46 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
52 u8 reg; in s5p_cec_enable_rx() local
54 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c59 printf("\n write reg 0x%08x = 0x%08x", addr, val); in dfs_reg_write()
71 u32 reg; in wait_refresh_op_complete() local
75 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
77 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
117 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
133 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
135 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
136 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
142 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
144 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-38x-controlcenterdc.dts60 reg = <0x00000000 0x10000000>; /* 256 MB */
80 reg = <0>;
97 reg = <0>; /* Chip select 0 */
104 reg = <1>; /* Chip select 1 */
116 reg = <0x21>;
123 reg = <0x22>;
129 reg = <0x23>;
135 reg = <0x24>;
141 reg = <0x25>;
147 reg = <0x26>;
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/riva/
H A Dnvreg.h44 #define DEVICE_ACCESS(device,reg) \ argument
45 nvCONTROL[(NV_##device##_##reg)/4]
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument
49 #define DEVICE_PRINT(device,reg) \ argument
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument
58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
[all …]
/OK3568_Linux_fs/kernel/arch/riscv/include/asm/
H A Dgdb_xml.h26 "<reg name=\""DBG_REG_ZERO"\" bitsize=\"64\" type=\"int\" regnum=\"0\"/>"
27 "<reg name=\""DBG_REG_RA"\" bitsize=\"64\" type=\"code_ptr\"/>"
28 "<reg name=\""DBG_REG_SP"\" bitsize=\"64\" type=\"data_ptr\"/>"
29 "<reg name=\""DBG_REG_GP"\" bitsize=\"64\" type=\"data_ptr\"/>"
30 "<reg name=\""DBG_REG_TP"\" bitsize=\"64\" type=\"data_ptr\"/>"
31 "<reg name=\""DBG_REG_T0"\" bitsize=\"64\" type=\"int\"/>"
32 "<reg name=\""DBG_REG_T1"\" bitsize=\"64\" type=\"int\"/>"
33 "<reg name=\""DBG_REG_T2"\" bitsize=\"64\" type=\"int\"/>"
34 "<reg name=\""DBG_REG_FP"\" bitsize=\"64\" type=\"data_ptr\"/>"
35 "<reg name=\""DBG_REG_S1"\" bitsize=\"64\" type=\"int\"/>"
[all …]
/OK3568_Linux_fs/u-boot/board/imx31_phycore/
H A Dlowlevel_init.S10 .macro REG reg, val macro
11 ldr r2, =\reg
16 .macro REG8 reg, val
17 ldr r2, =\reg
33 REG IPU_CONF, IPU_CONF_DI_EN
34 REG CCM_CCMR, 0x074B0BF5
38 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
39 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
41 …REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_…
43 REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
[all …]
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/jpegd/
H A Dhal_jpegd_vdpu2.c36 static MPP_RET jpegd_regs_init(JpegRegSet *reg) in jpegd_regs_init() argument
39 memset(reg, 0, sizeof(JpegRegSet)); in jpegd_regs_init()
40 reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0; in jpegd_regs_init()
41 reg->reg50_dec_ctrl.sw_dec_scmd_dis = DEC_SCMD_DISABLE; in jpegd_regs_init()
42 reg->reg50_dec_ctrl.sw_dec_latency = DEC_LATENCY_COMPENSATION; in jpegd_regs_init()
44 reg->reg54_endian.sw_dec_in_endian = DEC_BIG_ENDIAN; in jpegd_regs_init()
45 reg->reg54_endian.sw_dec_out_endian = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
46 reg->reg54_endian.sw_dec_strendian_e = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
47 reg->reg54_endian.sw_dec_outswap32_e = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
48 reg->reg54_endian.sw_dec_inswap32_e = 1; in jpegd_regs_init()
[all …]
/OK3568_Linux_fs/kernel/tools/perf/arch/csky/util/
H A Dunwind-libdw.c15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
22 dwarf_regs[0] = REG(A0); in libdw__arch_set_initial_registers()
23 dwarf_regs[1] = REG(A1); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(A2); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(A3); in libdw__arch_set_initial_registers()
26 dwarf_regs[4] = REG(REGS0); in libdw__arch_set_initial_registers()
27 dwarf_regs[5] = REG(REGS1); in libdw__arch_set_initial_registers()
28 dwarf_regs[6] = REG(REGS2); in libdw__arch_set_initial_registers()
29 dwarf_regs[7] = REG(REGS3); in libdw__arch_set_initial_registers()
30 dwarf_regs[8] = REG(REGS4); in libdw__arch_set_initial_registers()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.c48 u32 reg; in rt2400pci_bbp_write() local
56 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt2400pci_bbp_write()
57 reg = 0; in rt2400pci_bbp_write()
58 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); in rt2400pci_bbp_write()
59 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); in rt2400pci_bbp_write()
60 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); in rt2400pci_bbp_write()
61 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write()
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
72 u32 reg; in rt2400pci_bbp_read() local
82 * doesn't become available in time, reg will be 0xffffffff in rt2400pci_bbp_read()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/microchip/
H A Dencx24j600-regmap.c60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, in regmap_encx24j600_sfr_read() argument
64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()
65 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read()
71 if (reg < 0x80) { in regmap_encx24j600_sfr_read()
81 switch (reg) { in regmap_encx24j600_sfr_read()
104 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read()
112 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument
115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
116 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update()
120 { .tx_buf = &reg, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/mscc/
H A Docelot_vsc7514.c24 REG(ANA_ADVLEARN, 0x009000),
25 REG(ANA_VLANMASK, 0x009004),
26 REG(ANA_PORT_B_DOMAIN, 0x009008),
27 REG(ANA_ANAGEFIL, 0x00900c),
28 REG(ANA_ANEVENTS, 0x009010),
29 REG(ANA_STORMLIMIT_BURST, 0x009014),
30 REG(ANA_STORMLIMIT_CFG, 0x009018),
31 REG(ANA_ISOLATED_PORTS, 0x009028),
32 REG(ANA_COMMUNITY_PORTS, 0x00902c),
33 REG(ANA_AUTOAGE, 0x009030),
[all …]

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