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Searched +full:pwr +full:- +full:reg (Results 1 – 25 of 884) sorted by relevance

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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/
H A Dhalrf_pwr_table.c45 return -1; in halrf_get_predefined_pw_lmt_regu_type_from_str()
82 struct halrf_pwr_info *pwr = &rf->pwr_info; in halrf_get_regulation_info() local
84 u8 reg = REGULATION_NA; in halrf_get_regulation_info() local
100 if (pwr->regulation_idx != 0xff) in halrf_get_regulation_info()
101 return pwr->regulation_idx; in halrf_get_regulation_info()
104 reg = rg_info.regulation_2g; in halrf_get_regulation_info()
107 reg = rg_info.regulation_5g; in halrf_get_regulation_info()
121 if (reg == REGULATION_NA) in halrf_get_regulation_info()
123 pw_lmt_type = regulation_to_pw_lmt_regu_type(reg); in halrf_get_regulation_info()
126 if (pwr->regulation[band][pw_lmt_type] != true) { in halrf_get_regulation_info()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/
H A Dhalrf_pwr_table.c45 return -1; in halrf_get_predefined_pw_lmt_regu_type_from_str()
82 struct halrf_pwr_info *pwr = &rf->pwr_info; in halrf_get_regulation_info() local
84 u8 reg = REGULATION_NA; in halrf_get_regulation_info() local
100 if (pwr->regulation_idx != 0xff) in halrf_get_regulation_info()
101 return pwr->regulation_idx; in halrf_get_regulation_info()
104 reg = rg_info.regulation_2g; in halrf_get_regulation_info()
107 reg = rg_info.regulation_5g; in halrf_get_regulation_info()
121 if (reg == REGULATION_NA) in halrf_get_regulation_info()
123 pw_lmt_type = regulation_to_pw_lmt_regu_type(reg); in halrf_get_regulation_info()
126 if (pwr->regulation[band][pw_lmt_type] != true) { in halrf_get_regulation_info()
[all …]
/OK3568_Linux_fs/kernel/arch/x86/platform/intel-mid/
H A Dpwr.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * pci_platform_pm_ops (see drivers/pci/pci-mid.c).
27 #include <asm/intel-mid.h>
106 static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg) in mid_pwr_get_state() argument
108 return readl(pwr->regs + PM_SSS(reg)); in mid_pwr_get_state()
111 static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value) in mid_pwr_set_state() argument
113 writel(value, pwr->regs + PM_SSC(reg)); in mid_pwr_set_state()
116 static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value) in mid_pwr_set_wake() argument
118 writel(value, pwr->regs + PM_WKC(reg)); in mid_pwr_set_wake()
121 static void mid_pwr_interrupt_disable(struct mid_pwr *pwr) in mid_pwr_interrupt_disable() argument
[all …]
/OK3568_Linux_fs/kernel/drivers/input/misc/
H A Dmc13783-pwrbutton.c4 * Based on twl4030-pwrbutton driver by:
5 * Peter De Schrijver <peter.de-schrijver@nokia.com>
19 * Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335 USA
33 struct input_dev *pwr; member
60 mc13xxx_irq_ack(priv->mc13783, irq); in button_irq()
61 mc13xxx_reg_read(priv->mc13783, MC13783_REG_INTERRUPT_SENSE_1, &val); in button_irq()
66 if (priv->flags & MC13783_PWRB_B1_POL_INVERT) in button_irq()
68 input_report_key(priv->pwr, priv->keymap[0], val); in button_irq()
73 if (priv->flags & MC13783_PWRB_B2_POL_INVERT) in button_irq()
75 input_report_key(priv->pwr, priv->keymap[1], val); in button_irq()
[all …]
H A Dtps65218-pwrbutton.c4 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
6 * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
57 { .compatible = "ti,tps65217-pwrbutton", .data = &tps65217_data },
58 { .compatible = "ti,tps65218-pwrbutton", .data = &tps65218_data },
65 struct tps6521x_pwrbutton *pwr = _pwr; in tps6521x_pb_irq() local
66 const struct tps6521x_data *tps_data = pwr->data; in tps6521x_pb_irq()
67 unsigned int reg; in tps6521x_pb_irq() local
70 error = regmap_read(pwr->regmap, tps_data->reg_status, &reg); in tps6521x_pb_irq()
72 dev_err(pwr->dev, "can't read register: %d\n", error); in tps6521x_pb_irq()
76 if (reg & tps_data->pb_mask) { in tps6521x_pb_irq()
[all …]
H A Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
72 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
85 struct input_dev *pwr = _pwr; in pwrkey_press_irq() local
87 input_report_key(pwr, KEY_POWER, 1); in pwrkey_press_irq()
88 input_sync(pwr); in pwrkey_press_irq()
95 struct input_dev *pwr = _pwr; in pwrkey_release_irq() local
97 input_report_key(pwr, KEY_POWER, 0); in pwrkey_release_irq()
98 input_sync(pwr); in pwrkey_release_irq()
108 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
[all …]
/OK3568_Linux_fs/u-boot/board/samsung/trats/
H A Dtrats.c7 * SPDX-License-Identifier: GPL-2.0+
60 struct exynos4_power *pwr = in trats_low_power_mode() local
65 writel(0x0, &pwr->arm_core1_configuration); in trats_low_power_mode()
72 writel(0xa0c80604, &clk->apll_con0); in trats_low_power_mode()
79 writel(0x00000100, &clk->div_cpu0); in trats_low_power_mode()
81 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ in trats_low_power_mode()
82 while (readl(&clk->div_stat_cpu0) & 0x1111111) in trats_low_power_mode()
90 writel(0x13113117, &clk->div_dmc0); in trats_low_power_mode()
92 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ in trats_low_power_mode()
93 while (readl(&clk->div_stat_dmc0) & 0x11111111) in trats_low_power_mode()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/regulator/
H A Dst,stm32mp1-pwr-reg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/st,stm32mp1-pwr-reg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STM32MP1 PWR voltage regulators
10 - Pascal Paillet <p.paillet@st.com>
14 const: st,stm32mp1,pwr-reg
16 reg:
19 vdd-supply:
22 vdd_3v3_usbfs-supply:
[all …]
/OK3568_Linux_fs/u-boot/board/toradex/apalis-tk1/
H A Das3722_init.c2 * Copyright (c) 2012-2016 Toradex, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch-tegra/tegra_i2c.h>
12 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
16 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; in tegra_i2c_ll_write_addr() local
18 writel(addr, &reg->cmd_addr0); in tegra_i2c_ll_write_addr()
19 writel(config, &reg->cnfg); in tegra_i2c_ll_write_addr()
24 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; in tegra_i2c_ll_write_data() local
26 writel(data, &reg->cmd_data1); in tegra_i2c_ll_write_data()
27 writel(config, &reg->cnfg); in tegra_i2c_ll_write_data()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rtc/
H A Disil,isl12026.txt5 at bus address 0x57. The canonical "reg" value will be for the RTC portion.
9 - "compatible": must be "isil,isl12026"
10 - "reg": I2C bus address of the device (always 0x6f)
14 - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
17 - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
25 reg = <0x6f>;
26 isil,pwr-bsw = <0>;
27 isil,pwr-sbib = <1>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
[all …]
/OK3568_Linux_fs/u-boot/board/nvidia/venice2/
H A Das3722_init.c5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch-tegra/tegra_i2c.h>
13 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
17 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; in tegra_i2c_ll_write_addr() local
19 writel(addr, &reg->cmd_addr0); in tegra_i2c_ll_write_addr()
20 writel(config, &reg->cnfg); in tegra_i2c_ll_write_addr()
25 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; in tegra_i2c_ll_write_data() local
27 writel(data, &reg->cmd_data1); in tegra_i2c_ll_write_data()
28 writel(config, &reg->cnfg); in tegra_i2c_ll_write_data()
37 debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__); in pmic_enable_cpu_vdd()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/samsung/
H A Dphy-s5pv210-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
12 #include "phy-samsung-usb2.h"
70 static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg) in s5pv210_rate_to_clk() argument
74 *reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ; in s5pv210_rate_to_clk()
77 *reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ; in s5pv210_rate_to_clk()
80 *reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ; in s5pv210_rate_to_clk()
83 return -EINVAL; in s5pv210_rate_to_clk()
91 struct samsung_usb2_phy_driver *drv = inst->drv; in s5pv210_isol()
94 switch (inst->cfg->id) { in s5pv210_isol()
[all …]
H A Dphy-exynos4210-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support
13 #include "phy-samsung-usb2.h"
87 /* Mode switching SUB Device <-> Host */
105 static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg) in exynos4210_rate_to_clk() argument
109 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ; in exynos4210_rate_to_clk()
112 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ; in exynos4210_rate_to_clk()
115 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ; in exynos4210_rate_to_clk()
118 return -EINVAL; in exynos4210_rate_to_clk()
126 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4210_isol()
[all …]
H A Dphy-exynos4x12-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
13 #include "phy-samsung-usb2.h"
114 /* Mode switching SUB Device <-> Host */
132 static int exynos4x12_rate_to_clk(unsigned long rate, u32 *reg) in exynos4x12_rate_to_clk() argument
138 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6; in exynos4x12_rate_to_clk()
141 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ; in exynos4x12_rate_to_clk()
144 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ; in exynos4x12_rate_to_clk()
147 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2; in exynos4x12_rate_to_clk()
150 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ; in exynos4x12_rate_to_clk()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpu/
H A Dnvidia,gk20a.txt4 - compatible: "nvidia,<gpu>"
6 - nvidia,gk20a
7 - nvidia,gm20b
8 - nvidia,gp10b
9 - nvidia,gv11b
10 - reg: Physical base address and length of the controller's registers.
12 - first entry for bar0
13 - second entry for bar1
14 - interrupts: Must contain an entry for each entry in interrupt-names.
15 See ../interrupt-controller/interrupts.txt for details.
[all …]
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dtegra_mmc.c5 * Portions Copyright 2011-2016 NVIDIA Corporation
7 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch-tegra/tegra_mmc.h>
27 struct tegra_mmc *reg; member
40 u8 pwr = 0; in tegra_mmc_set_power() local
43 if (power != (unsigned short)-1) { in tegra_mmc_set_power()
46 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; in tegra_mmc_set_power()
50 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; in tegra_mmc_set_power()
54 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; in tegra_mmc_set_power()
58 debug("%s: pwr = %X\n", __func__, pwr); in tegra_mmc_set_power()
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/typec/tcpm/
H A Dtcpci_husb311.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Wang Jie <dave.wang@rock-chips.com>
6 * Hynetek Husb311 Type-C Chip Driver
35 static int husb311_read8(struct husb311_chip *chip, unsigned int reg, u8 *val) in husb311_read8() argument
37 return regmap_raw_read(chip->data.regmap, reg, val, sizeof(u8)); in husb311_read8()
40 static int husb311_write8(struct husb311_chip *chip, unsigned int reg, u8 val) in husb311_write8() argument
42 return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u8)); in husb311_write8()
45 static int husb311_write16(struct husb311_chip *chip, unsigned int reg, u16 val) in husb311_write16() argument
47 return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u16)); in husb311_write16()
80 dev_err(chip->dev, "fail to init registers(%d)\n", ret); in husb311_init()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_set_pwr_table_8852b.c45 for (i = n - 1; i >= 0; i--) { in _halrf_bub_sort_8852b()
65 struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; in halrf_set_power_by_rate_to_struct_8852b()
66 struct rtw_tpu_pwr_by_rate_info *rate = &tpu->rtw_tpu_pwr_by_rate_i; in halrf_set_power_by_rate_to_struct_8852b()
71 …rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK1, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
72 …rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK2, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
73 …rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK5_5, 0, 0… in halrf_set_power_by_rate_to_struct_8852b()
74 …rate->pwr_by_rate_lgcy[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0)… in halrf_set_power_by_rate_to_struct_8852b()
76 …rate->pwr_by_rate_lgcy[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM6, 0, 0)… in halrf_set_power_by_rate_to_struct_8852b()
77 …rate->pwr_by_rate_lgcy[5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM9, 0, 0)… in halrf_set_power_by_rate_to_struct_8852b()
78 …rate->pwr_by_rate_lgcy[6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM12, 0, 0… in halrf_set_power_by_rate_to_struct_8852b()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_set_pwr_table_8852b.c45 for (i = n - 1; i >= 0; i--) { in _halrf_bub_sort_8852b()
65 struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; in halrf_set_power_by_rate_to_struct_8852b()
66 struct rtw_tpu_pwr_by_rate_info *rate = &tpu->rtw_tpu_pwr_by_rate_i; in halrf_set_power_by_rate_to_struct_8852b()
71 …rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK1, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
72 …rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK2, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
73 …rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK5_5, 0, 0… in halrf_set_power_by_rate_to_struct_8852b()
74 …rate->pwr_by_rate_lgcy[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0)… in halrf_set_power_by_rate_to_struct_8852b()
76 …rate->pwr_by_rate_lgcy[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM6, 0, 0)… in halrf_set_power_by_rate_to_struct_8852b()
77 …rate->pwr_by_rate_lgcy[5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM9, 0, 0)… in halrf_set_power_by_rate_to_struct_8852b()
78 …rate->pwr_by_rate_lgcy[6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM12, 0, 0… in halrf_set_power_by_rate_to_struct_8852b()
[all …]
/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-isl12026.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/nvmem-provider.h>
43 static int isl12026_read_reg(struct i2c_client *client, int reg) in isl12026_read_reg() argument
45 u8 addr[] = {0, reg}; in isl12026_read_reg()
51 .addr = client->addr, in isl12026_read_reg()
56 .addr = client->addr, in isl12026_read_reg()
63 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); in isl12026_read_reg()
65 dev_err(&client->dev, "read reg error, ret=%d\n", ret); in isl12026_read_reg()
66 ret = ret < 0 ? ret : -EIO; in isl12026_read_reg()
79 .addr = client->addr, in isl12026_arm_write()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ata/
H A Dahci-st.txt6 - compatible : Must be "st,ahci"
7 - reg : Physical base addresses and length of register sets
8 - interrupts : Interrupt associated with the SATA device
9 - interrupt-names : Associated name must be; "hostc"
10 - clocks : The phandle for the clock
11 - clock-names : Associated name must be; "ahci_clk"
12 - phys : The phandle for the PHY port
13 - phy-names : Associated name must be; "ahci_phy"
16 - resets : The power-down, soft-reset and power-reset lines of SATA IP
17 - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/tegra/
H A Dflowctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
74 unsigned int reg; in flowctrl_cpu_suspend_enter() local
77 reg = flowctrl_read_cpu_csr(cpuid); in flowctrl_cpu_suspend_enter()
81 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; in flowctrl_cpu_suspend_enter()
83 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; in flowctrl_cpu_suspend_enter()
84 /* pwr gating on wfe */ in flowctrl_cpu_suspend_enter()
85 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; in flowctrl_cpu_suspend_enter()
91 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; in flowctrl_cpu_suspend_enter()
93 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; in flowctrl_cpu_suspend_enter()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darmada-xp-synology-ds414.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-xp-mv78230.dtsi"
29 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
30 "marvell,armadaxp", "marvell,armada-370-xp";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-xp-synology-ds414.dts13 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
16 * were delivered with an older version of u-boot that left internal
21 * installing it from u-boot prompt) or adjust the Devive Tree
25 /dts-v1/;
27 #include <dt-bindings/input/input.h>
28 #include <dt-bindings/gpio/gpio.h>
29 #include "armada-xp-mv78230.dtsi"
33 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
34 "marvell,armadaxp", "marvell,armada-370-xp";
38 stdout-path = &uart0;
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