5  * SPDX-License-Identifier:     GPL-2.0+
10 #include <asm/arch-tegra/tegra_i2c.h>
13 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
17 	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;  in tegra_i2c_ll_write_addr()  local
19 	writel(addr, &reg->cmd_addr0);  in tegra_i2c_ll_write_addr()
20 	writel(config, &reg->cnfg);  in tegra_i2c_ll_write_addr()
25 	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;  in tegra_i2c_ll_write_data()  local
27 	writel(data, &reg->cmd_data1);  in tegra_i2c_ll_write_data()
28 	writel(config, &reg->cnfg);  in tegra_i2c_ll_write_data()
37 	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);  in pmic_enable_cpu_vdd()
38 	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */  in pmic_enable_cpu_vdd()
42 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.  in pmic_enable_cpu_vdd()
48 	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);  in pmic_enable_cpu_vdd()
50 	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.  in pmic_enable_cpu_vdd()
56 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.  in pmic_enable_cpu_vdd()
61 	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);  in pmic_enable_cpu_vdd()
63 	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.  in pmic_enable_cpu_vdd()
69 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.  in pmic_enable_cpu_vdd()
74 	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);  in pmic_enable_cpu_vdd()
76 	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.  in pmic_enable_cpu_vdd()
82 	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.  in pmic_enable_cpu_vdd()
87 	debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);  in pmic_enable_cpu_vdd()
89 	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.  in pmic_enable_cpu_vdd()
98 	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.  in pmic_enable_cpu_vdd()