Home
last modified time | relevance | path

Searched full:pll4 (Results 1 – 25 of 61) sorted by relevance

123

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun9i-a80-pll4-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
20 const: allwinner,sun9i-a80-pll4-clk
44 compatible = "allwinner,sun9i-a80-pll4-clk";
47 clock-output-names = "pll4";
H A Dallwinner,sun9i-a80-apb0-clk.yaml50 clocks = <&osc24M>, <&pll4>;
59 clocks = <&osc24M>, <&pll4>;
H A Dallwinner,sun4i-a10-ve-clk.yaml51 clocks = <&pll4>;
H A Dallwinner,sun9i-a80-ahb-clk.yaml48 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
H A Dallwinner,sun9i-a80-gt-clk.yaml48 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
H A Dallwinner,sun9i-a80-cpus-clk.yaml48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
H A Dallwinner,sun4i-a10-mmc-clk.yaml82 clocks = <&osc24M>, <&pll4>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun9i-a80.dtsi193 pll4: clk@0600000c { label
195 compatible = "allwinner,sun9i-a80-pll4-clk";
198 clock-output-names = "pll4";
203 compatible = "allwinner,sun9i-a80-pll4-clk";
213 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
221 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
229 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
237 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
245 clocks = <&osc24M>, <&pll4>;
253 clocks = <&osc24M>, <&pll4>;
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dlcc-ipq806x.c26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
394 [PLL4] = &pll4.clkr,
437 /* Configure the rate of PLL4 if the bootloader hasn't already */ in lcc_ipq806x_probe()
440 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true); in lcc_ipq806x_probe()
441 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_ipq806x_probe()
H A Dlcc-msm8960.c26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
479 [PLL4] = &pll4.clkr,
543 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_msm8960_probe()
554 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_msm8960_probe()
H A Dlcc-mdm9615.c28 static struct clk_pll pll4 = { variable
37 .name = "pll4",
481 [PLL4] = &pll4.clkr,
544 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_mdm9615_probe()
555 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_mdm9615_probe()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-audio.yaml17 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
23 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
32 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
H A Dti,j721e-cpb-ivi-audio.yaml22 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
26 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
29 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sun9i-core.c18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
19 * PLL4 rate is calculated as follows
82 pr_err("Could not get registers for a80-pll4-clk: %pOFn\n", in sun9i_a80_pll4_setup()
90 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
H A Dclk-sun9i-cpus.c62 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
86 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dqcom,lcc-ipq806x.h9 #define PLL4 0 macro
H A Dqcom,lcc-msm8960.h9 #define PLL4 0 macro
H A Dqcom,lcc-mdm9615.h11 #define PLL4 0 macro
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dstm32mp157c-odyssey.dts35 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h23 u32 pll4_cfg; /* 0x18 pll4 ve control */
98 u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */
H A Dclock_sun6i.h21 u32 pll4_cfg; /* 0x18 pll4 control */
126 u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
140 u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
/OK3568_Linux_fs/kernel/sound/soc/ti/
H A Dj721e-evm.c205 clk_id == J721E_CLK_PARENT_48000 ? "PLL4" : "PLL15", in j721e_configure_refclk()
521 [J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */
530 [J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */
538 [J721E_CLK_PARENT_48000] = 2359296000u, /* PLL4 */
/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Dr8a774b1-cpg-mssr.c59 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
245 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
H A Dr8a77965-cpg-mssr.c63 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
275 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
H A Dr8a774a1-cpg-mssr.c61 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
249 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC

123