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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/
H A Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
30 operating-points-v2 = <&bus_gscl_opp_table>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/opp/
H A Dopp.txt1 Generic OPP (Operating Performance Points) Bindings
2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
5 have the liberty of choosing these. These combinations are called Operating
6 Performance Points aka OPPs. This document defines bindings for these OPPs
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
27 compatible = "arm,cortex-a9";
[all …]
H A Dqcom-nvmem-cpufreq.txt8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
26 --------------------
28 - power-domains: A phandle pointing to the PM domain specifier which provides
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-op1-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <800000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000>;
[all …]
H A Drk3399-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include "rk3399-sched-energy.dtsi"
9 cluster0_opp: opp-table0 {
10 compatible = "operating-points-v2";
11 opp-shared;
13 rockchip,temp-hysteresis = <5000>;
14 rockchip,low-temp = <10000>;
15 rockchip,low-temp-min-volt = <900000>;
17 nvmem-cells = <&cpul_leakage>, <&specification_serial_number>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
23 stdout-path = "serial2:115200n8";
27 compatible = "samsung,secure-firmware";
31 fixed-rate-clocks {
[all …]
H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a9";
40 clock-names = "cpu";
41 clock-latency = <160000>;
43 operating-points = <
[all …]
H A Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a9";
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a15";
30 clock-frequency = <1800000000>;
31 cci-control-port = <&cci_control1>;
32 operating-points-v2 = <&cluster_a15_opp_table>;
[all …]
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-a7";
29 clock-frequency = <1000000000>;
30 cci-control-port = <&cci_control0>;
31 operating-points-v2 = <&cluster_a7_opp_table>;
[all …]
H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
[all …]
H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
25 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
[all …]
H A Dti-cpufreq.txt6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
8 used to determine which OPPs from the operating-points-v2 table get enabled
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,
20 - syscon: A phandle pointing to a syscon node representing the control module
24 --------------------
25 - "vdd-supply", "vbb-supply": to define two regulators for dra7xx
[all …]
H A Dnvidia,tegra20-cpufreq.txt5 - clocks: Must contain an entry for the CPU clock.
6 See ../clocks/clock-bindings.txt for details.
7 - operating-points-v2: See ../bindings/opp/opp.txt for details.
8 - #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
10 For each opp entry in 'operating-points-v2' table:
11 - opp-supported-hw: Two bitfields indicating:
23 - opp-microvolt: CPU voltage triplet.
26 - cpu-supply: Phandle to the CPU power supply.
31 regulator-name = "vdd_cpu";
36 compatible = "operating-points-v2";
[all …]
H A Dcpufreq-rockchip.txt6 with 'prop' information which is used to determine opp-microvolt-<name>
8 on operating-points-v2, but the driver can also create the "cpufreq-dt"
9 platform_device to compatibility with operating-points.
14 In 'operating-points-v2' table:
15 - rockchip,leakage-voltage-sel: The property is an array of 3-tuples items, and
17 <min-leakage max-leakage volt-selector>.
18 min-leakage: minimum leakage in mA, ranges from 1 to 254.
19 max-leakage: maximum leakage in mA, ranges from 1 to 254.
20 voltage-selector: a sequence number which is used to math
21 opp-microvolt-L<number> roperty in OPP node.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/
H A Dqcom,rpmpd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rajendra Nayak <rnayak@codeaurora.org>
19 - qcom,msm8976-rpmpd
20 - qcom,msm8996-rpmpd
21 - qcom,msm8998-rpmpd
22 - qcom,qcs404-rpmpd
23 - qcom,sc7180-rpmhpd
24 - qcom,sdm845-rpmhpd
[all …]
H A Dmali-opp.txt1 # SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 # (C) COPYRIGHT 2017, 2019-2021 ARM Limited. All rights reserved.
17 # http://www.gnu.org/licenses/gpl-2.0.html.
30 - compatible: Allow OPPs to express their compatibility. It should be:
31 "operating-points-v2", "operating-points-v2-mali".
33 - OPP nodes: One or more OPP nodes describing voltage-current-frequency
39 This defines voltage-current-frequency combinations along with other related
43 - opp-hz: Nominal frequency in Hz, expressed as a 64-bit big-endian integer.
48 - opp-hz-real: List of one or two real frequencies in Hz, expressed as 64-bit
49 big-endian integers. They shall correspond to the clocks declared under
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/devfreq/
H A Dexynos-bus.txt4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
28 |--- C block (passive)
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 vddcpu_a: regulator-vddcpu-a {
15 compatible = "pwm-regulator";
17 regulator-name = "VDDCPU_A";
18 regulator-min-microvolt = <690000>;
19 regulator-max-microvolt = <1050000>;
21 pwm-supply = <&dc_in>;
24 pwm-dutycycle-range = <100 0>;
26 regulator-boot-on;
27 regulator-always-on;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 cpu0_opp_table: opp-table-cpu {
8 compatible = "operating-points-v2";
9 opp-shared;
11 opp-648000000 {
12 opp-hz = /bits/ 64 <648000000>;
13 opp-microvolt = <1040000>;
14 clock-latency-ns = <244144>; /* 8 32k periods */
17 opp-816000000 {
18 opp-hz = /bits/ 64 <816000000>;
[all …]
H A Dsun50i-h5-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
5 cpu_opp_table: opp-table-cpu {
6 compatible = "operating-points-v2";
7 opp-shared;
9 opp-408000000 {
10 opp-hz = /bits/ 64 <408000000>;
11 opp-microvolt = <1000000 1000000 1310000>;
12 clock-latency-ns = <244144>; /* 8 32k periods */
15 opp-648000000 {
[all …]
H A Dsun50i-h6-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 cpu_opp_table: opp-table-cpu {
7 compatible = "allwinner,sun50i-h6-operating-points";
8 nvmem-cells = <&cpu_speed_grade>;
9 opp-shared;
12 clock-latency-ns = <244144>; /* 8 32k periods */
13 opp-hz = /bits/ 64 <480000000>;
15 opp-microvolt-speed0 = <880000 880000 1200000>;
16 opp-microvolt-speed1 = <820000 820000 1200000>;
17 opp-microvolt-speed2 = <820000 820000 1200000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dsdm845.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sdm845.h>
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/
H A Dgpu.txt4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
5 "amd,imageon-XYZ.W", "amd,imageon"
6 for example: "qcom,adreno-306.0", "qcom,adreno"
9 with the chip-id.
11 - reg: Physical base address and length of the controller's registers.
12 - interrupts: The interrupt signal from the gpu.
13 - clocks: device clocks (if applicable)
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names: the following clocks are required by a3xx, a4xx and a5xx
22 - qcom,adreno-630.2
[all …]

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