| /OK3568_Linux_fs/u-boot/board/sbc8548/ |
| H A D | tlb.c | 7 * SPDX-License-Identifier: GPL-2.0+
14 /* TLB 0 - for temp stack in cache */
32 * TLB 0: 64M Non-cacheable, guarded
34 * 0xff800000 8M boot FLASH
36 * 0xfc000000 64M user flash
45 * TLB 1: 1G Non-cacheable, guarded
54 * TLB 2: 64M Non-cacheable, guarded
65 * TLB 3: 64M Cacheable, non-guarded
73 * TLB 4: 64M Cacheable, non-guarded
83 * TLB 5: 16M Cacheable, non-guarded
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| /OK3568_Linux_fs/u-boot/doc/ |
| H A D | README.ti-secure | 22 Booting of U-Boot SPL
25 When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process
36 ${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
38 This is called as part of the SPL/u-boot build process. As the secure
49 create-boot-image.sh \
55 SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
56 X-LOADER - Generates an image for non-XIP flash
57 MLO - Generates an image for SD/MMC/eMMC media
58 2ND - Generates an image for USB, UART and Ethernet
59 XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
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| H A D | README.update | 5 --------
8 server in NOR Flash. In more detail: a TFTP transfer of a file given in
11 updates. Each update in the update file has an address in NOR Flash where it
12 should be placed, updates are also protected with a SHA-1 checksum. If the
14 verification is positive, the update is stored in Flash.
16 The auto-update feature is enabled by the CONFIG_UPDATE_TFTP macro:
21 Note that when enabling auto-update, Flash support must be turned on. Also,
27 The auto-update feature uses the following configuration knobs:
29 - CONFIG_UPDATE_LOAD_ADDR
36 - CONFIG_UPDATE_TFTP_CNT_MAX
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| /OK3568_Linux_fs/u-boot/include/configs/ |
| H A D | xpedite537x.h | 3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
90 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
91 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
92 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
93 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
94 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
95 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
96 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
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| H A D | xpedite517x.h | 3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
73 * Base addresses -- Note these are effective addresses where the
96 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
97 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
98 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
99 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
100 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
101 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
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| H A D | xpedite520x.h | 3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
77 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
78 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
79 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
80 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
81 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
82 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
83 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
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| H A D | xpedite550x.h | 3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
94 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
95 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
96 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
97 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
98 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
99 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
100 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
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| H A D | MPC8548CDS.h | 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
4 * SPDX-License-Identifier: GPL-2.0+
29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
96 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
97 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
98 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
100 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
101 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
102 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
109 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
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| H A D | MPC8544DS.h | 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
83 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
85 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
87 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
88 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
95 * Localbus non-cacheable
97 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
98 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
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| H A D | P1023RDB.h | 4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
34 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
78 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
79 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
80 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
82 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
85 * Localbus non-cacheable
87 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
88 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
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| H A D | edb93xx.h | 2 * U-Boot - Configuration file for Cirrus Logic EDB93xx boards
34 #define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
72 /* High-level configuration options */
109 * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
110 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
111 * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
114 * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
123 * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
124 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
125 * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
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| H A D | P1010RDB.h | 2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
75 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
76 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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| /OK3568_Linux_fs/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 5 The P1010 is a cost-effective, low-power, highly integrated host processor
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
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| H A D | README.P1010RDB-PB | 3 The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
4 P1010RDB-PB is a variation of previous P1010RDB-PA board.
6 The P1010 is a cost-effective, low-power, highly integrated host processor
13 The P1010RDB-PB board features are as following:
15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
16 - 32M bytes NOR flash single-chip memory
17 - 2G bytes NAND flash memory
18 - 16M bytes SPI memory
19 - 256K bit M24256 I2C EEPROM
20 - I2C Board EEPROM 128x8 bit memory
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| /OK3568_Linux_fs/u-boot/drivers/mtd/ |
| H A D | Kconfig | 11 flash, RAM and similar chips, often used for solid state file
28 bool "Enable parallel NOR flash support"
30 Enable support for parallel NOR flash.
39 bool "Enable CFI Flash driver"
41 The Common Flash Interface specification was developed by Intel,
42 AMD and other flash manufactures. It provides a universal method
43 for probing the capabilities of flash devices. If you wish to
44 support any device that is CFI-compliant, you need to enable this
49 bool "Enable Driver Model for CFI Flash driver"
52 The Common Flash Interface specification was developed by Intel,
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| /OK3568_Linux_fs/kernel/Documentation/ABI/testing/ |
| H A D | sysfs-class-mtd | 4 Contact: linux-mtd@lists.infradead.org
12 Contact: linux-mtd@lists.infradead.org
16 physical/simulated flash devices, partitions on a flash
17 device, or concatenated flash devices.
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
39 Contact: linux-mtd@lists.infradead.org
42 to the read-only variant of thie MTD device (in
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| /OK3568_Linux_fs/u-boot/arch/x86/include/asm/ |
| H A D | mrccache.h | 5 * SPDX-License-Identifier: GPL-2.0+
34 * mrccache_find_current() - find the latest MRC cache record
39 * @entry: Position and size of MRC cache in SPI flash
45 * mrccache_update() - update the MRC cache with a new record
50 * @sf: SPI flash to write to
51 * @entry: Position and size of MRC cache in SPI flash
53 * @return 0 if updated, -EEXIST if the record is the same as the latest
54 * record, -EINVAL if the record is not valid, other error if SPI write failed
60 * mrccache_reserve() - reserve MRC data on the stack
62 * This copies MRC data pointed by gd->arch.mrc_output to a new place on the
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| /OK3568_Linux_fs/kernel/drivers/mtd/chips/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
6 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
10 The Common Flash Interface specification was developed by Intel,
11 AMD and other flash manufactures that provides a universal method
12 for probing the capabilities of flash devices. If you wish to
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
23 compatible with the Common Flash Interface, but will use the common
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| /OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_spl_loaders.c | 8 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; in nand_spl_load_image()
26 dst = (void *)((int)dst - page_offset); in nand_spl_load_image()
46 * Temporary storage for non NAND page aligned and non NAND page sized
47 * reads. Note: This does not support runtime detected FLASH yet, but
54 * nand_spl_read_block - Read data from physical eraseblock into a buffer
69 * To support runtime detected flash this needs to be extended by
70 * information about the actual flash geometry, but thats beyond the
81 /* Offset to the start of a flash page */ in nand_spl_read_block()
86 * Non page aligned reads go to the scratch buffer. in nand_spl_read_block()
91 read = min(len, CONFIG_SYS_NAND_PAGE_SIZE - offset); in nand_spl_read_block()
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| /OK3568_Linux_fs/u-boot/cmd/fastboot/ |
| H A D | Kconfig | 30 See doc/README.android-fastboot for more information.
71 bool "Enable FASTBOOT FLASH command"
73 The fastboot protocol includes a "flash" command for writing
74 the downloaded image to a non-volatile storage device. Define
75 this to enable the "fastboot flash" command.
78 int "Define FASTBOOT MMC FLASH default device"
81 The fastboot "flash" command requires additional information
82 regarding the non-volatile storage device. Define this to
|
| /OK3568_Linux_fs/kernel/drivers/mtd/devices/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Self-contained MTD device drivers"
12 These devices come in memory configurations from 32M - 1G. If you
41 tristate "DEC MS02-NV NVRAM module support"
44 This is an MTD driver for the DEC's MS02-NV (54-20948-01) battery
45 backed-up NVRAM module. The module was originally meant as an NFS
52 The module will be called ms02-nv.
59 Sometimes DataFlash chips are packaged inside MMC-format
66 This adds an extra check when data is written to the flash.
77 one-time-programmable (OTP) data. The first half may be written
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| /OK3568_Linux_fs/kernel/Documentation/networking/devlink/ |
| H A D | ice.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 .. list-table:: devlink info versions implemented
18 * - Name
19 - Type
20 - Example
21 - Description
22 * - ``board.id``
23 - fixed
24 - K65390-000
25 - The Product Board Assembly (PBA) identifier of the board.
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| /OK3568_Linux_fs/kernel/Documentation/leds/ |
| H A D | leds-class-flash.rst | 2 Flash LED handling under Linux
5 Some LED devices provide two modes - torch and flash. In the LED subsystem
6 those modes are supported by LED class (see Documentation/leds/leds-class.rst)
7 and LED Flash class respectively. The torch mode related features are enabled
8 by default and the flash ones only if a driver declares it by setting
11 In order to enable the support for flash LEDs CONFIG_LEDS_CLASS_FLASH symbol
12 must be defined in the kernel config. A LED Flash class driver must be
15 Following sysfs attributes are exposed for controlling flash LED devices:
16 (see Documentation/ABI/testing/sysfs-class-led-flash)
18 - flash_brightness
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| /OK3568_Linux_fs/kernel/drivers/mtd/maps/ |
| H A D | sc520cdp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform
4 * Copyright (C) 2001 Sysgo Real-Time Solutions GmbH
7 * from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
8 * and up to 512 KiB of 8-bit DIL Flash ROM.
22 ** The Embedded Systems BIOS decodes the first FLASH starting at
24 ** the flash at this location causes the A22 address line to be high
26 ** order address line on the raw flash devices themselves!!
27 ** This causes the top HALF of the flash to be accessed first. Beyond
28 ** the physical limits of the flash, the flash chip aliases over (to
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| /OK3568_Linux_fs/kernel/Documentation/arm/sa1100/ |
| H A D | assabet.rst | 2 The Intel Assabet (SA-1110 evaluation) board
13 -------------------
25 -----------------------
39 John Dorsey has produced add-on patches to add support for Assabet and
52 you need to have RedBoot installed in your flash memory. A known to work
55 - ftp://ftp.netwinder.org/users/n/nico/
56 - ftp://ftp.arm.linux.org.uk/pub/linux/arm/people/nico/
57 - ftp://ftp.handhelds.org/pub/linux/arm/sa-1100-patches/
59 Look for redboot-assabet*.tgz. Some installation infos are provided in
60 redboot-assabet*.txt.
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