include/configs/MPC8548CDS.h

2  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
4  * SPDX-License-Identifier:	GPL-2.0+
29 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
96  * 0xe000_0000	0xe00f_ffff	CCSR			1M	non-cacheable
97  * 0xe200_0000	0xe20f_ffff	PCI1 IO			1M	non-cacheable
98  * 0xe300_0000	0xe30f_ffff	PCIe IO			1M	non-cacheable
100  * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS		1M	non-cacheable
101  * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
102  * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M	non-cacheable
109  * 0xfe000_0000	0xfe00f_ffff	CCSR			1M	non-cacheable
110  * 0xfe200_0000	0xfe20f_ffff	PCI1 IO			1M	non-cacheable
111  * 0xfe300_0000	0xfe30f_ffff	PCIe IO			1M	non-cacheable
113  * 0xff800_0000	0xff80f_ffff	NVRAM/CADMUS		1M	non-cacheable
114  * 0xfff00_0000	0xfff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
115  * 0xfff80_0000	0xfffff_ffff	FLASH (boot bank)	8M	non-cacheable
124  * FLASH on the Local Bus
153 #define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
173 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
174 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
201  *    port-size = 32-bits = BR2[19:20] = 11
223  *    9 columns OR2[19-21] = 010
224  *    13 rows	OR2[23-25] = 100
259  *    port-size = 8-bits  = BR[19:20] = 01
299 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
336  * Memory space is mapped 1-1, but I/O space must start from 0.
433 /* Options are: eTSEC[0-3] */
443 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
465 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
496 #define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */
532    "bootm $loadaddr - $fdtaddr"