include/configs/P1010RDB.h

2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
4  * SPDX-License-Identifier:	GPL-2.0+
20 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
30 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
45 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
55 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
68 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
75 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
76 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
79 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
106 #define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
108 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
141 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
145  * Memory space is mapped 1-1, but I/O space must start from 0.
288  * 0x8000_0000  0xbfff_ffff	PCI Express Mem		1.5G non-cacheable
289  * 0xffc0_0000  0xffc3_ffff	PCI IO range		256k non-cacheable
291  * Localbus non-cacheable
292  * 0xff80_0000	0xff8f_ffff	NAND Flash		1M non-cacheable
293  * 0xffb0_0000	0xffbf_ffff	Board CPLD		1M non-cacheable
295  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
301 /* NOR Flash on IFC */
318 /* NOR Flash Timing Params */
335 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
336 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
338 /* CFI for NOR Flash */
344 /* NAND Flash on IFC */
353 #define MTDIDS_DEFAULT			"nand0=ff800000.flash"
355 	"mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
366 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
377 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
389 /* NAND Flash Timing Params */
404 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
405 /* ONFI NAND Flash mode0 Timing Params */
502 						- GENERATED_GBL_DATA_SIZE)
539 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
540 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
599 /* eSPI - Enhanced SPI */
699 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
702 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
720 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
748 #define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */