1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/mmu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 14*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 17*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 21*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 22*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 25*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 26*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 29*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * TLB 0: 64M Non-cacheable, guarded 33*4882a593Smuzhiyun * 0xfc000000 56M unused 34*4882a593Smuzhiyun * 0xff800000 8M boot FLASH 35*4882a593Smuzhiyun * .... or .... 36*4882a593Smuzhiyun * 0xfc000000 64M user flash 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * Out of reset this entry is only 4K. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, 41*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_64M, 1), 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * TLB 1: 1G Non-cacheable, guarded 46*4882a593Smuzhiyun * 0x80000000 512M PCI1 MEM 47*4882a593Smuzhiyun * 0xa0000000 512M PCIe MEM 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 50*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_1G, 1), 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * TLB 2: 64M Non-cacheable, guarded 55*4882a593Smuzhiyun * 0xe0000000 1M CCSRBAR 56*4882a593Smuzhiyun * 0xe2000000 8M PCI1 IO 57*4882a593Smuzhiyun * 0xe2800000 8M PCIe IO 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 60*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_64M, 1), 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifdef CONFIG_SYS_LBC_SDRAM_BASE 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * TLB 3: 64M Cacheable, non-guarded 66*4882a593Smuzhiyun * 0xf0000000 64M LBC SDRAM First half 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, 69*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 70*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_64M, 1), 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * TLB 4: 64M Cacheable, non-guarded 74*4882a593Smuzhiyun * 0xf4000000 64M LBC SDRAM Second half 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, 77*4882a593Smuzhiyun CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, 78*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 79*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_64M, 1), 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * TLB 5: 16M Cacheable, non-guarded 84*4882a593Smuzhiyun * 0xf8000000 1M 7-segment LED display 85*4882a593Smuzhiyun * 0xf8100000 1M User switches 86*4882a593Smuzhiyun * 0xf8300000 1M Board revision 87*4882a593Smuzhiyun * 0xf8b00000 1M EEPROM 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, 90*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 91*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_16M, 1), 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #ifndef CONFIG_SYS_ALT_BOOT 94*4882a593Smuzhiyun /* 95*4882a593Smuzhiyun * TLB 6: 64M Non-cacheable, guarded 96*4882a593Smuzhiyun * 0xec000000 64M 64MB user FLASH 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, 99*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_64M, 1), 101*4882a593Smuzhiyun #else 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * TLB 6: 4M Non-cacheable, guarded 104*4882a593Smuzhiyun * 0xef800000 4M 1st 1/2 8MB soldered FLASH 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, 107*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 108*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_4M, 1), 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * TLB 7: 4M Non-cacheable, guarded 112*4882a593Smuzhiyun * 0xefc00000 4M 2nd half 8MB soldered FLASH 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, 115*4882a593Smuzhiyun CONFIG_SYS_ALT_FLASH + 0x400000, 116*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 117*4882a593Smuzhiyun 0, 7, BOOKE_PAGESZ_4M, 1), 118*4882a593Smuzhiyun #endif 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 123