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/OK3568_Linux_fs/kernel/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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/OK3568_Linux_fs/kernel/sound/pci/trident/
H A Dtrident_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Trident 4DWave-NX memory page allocation (TLB area)
23 do { (trident)->tlb.entries[page] = cpu_to_le32((addr) & ~(SNDRV_TRIDENT_PAGE_SIZE-1)); \
24 (trident)->tlb.shadow_entries[page] = (ptr); } while (0)
26 (void*)((trident)->tlb.shadow_entries[page])
28 (dma_addr_t)le32_to_cpu((trident->tlb.entries[page]) & ~(SNDRV_TRIDENT_PAGE_SIZE - 1))
31 /* page size == SNDRV_TRIDENT_PAGE_SIZE */
32 #define ALIGN_PAGE_SIZE PAGE_SIZE /* minimum page size for allocation */
34 /* fill TLB entrie(s) corresponding to page with ptr */
36 /* fill TLB entrie(s) corresponding to page with silence pointer */
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/OK3568_Linux_fs/kernel/arch/sparc/mm/
H A Dhugetlbpage.c1 // SPDX-License-Identifier: GPL-2.0
3 * SPARC64 Huge TLB page support.
17 #include <asm/tlb.h>
22 /* Slightly simplified from the non-hugepage variant because by
48 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_bottomup()
64 struct mm_struct *mm = current->mm; in hugetlb_get_unmapped_area_topdown()
68 /* This should only ever run for 32-bit processes. */ in hugetlb_get_unmapped_area_topdown()
74 info.high_limit = mm->mmap_base; in hugetlb_get_unmapped_area_topdown()
81 * so fall back to the bottom-up function here. This scenario in hugetlb_get_unmapped_area_topdown()
86 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_topdown()
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/OK3568_Linux_fs/kernel/kernel/dma/
H A Dswiotlb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * I/O TLBs (aka DMA address translation hardware).
9 * Copyright (C) 2000, 2003 Hewlett-Packard Co
10 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
14 * unnecessary i-cache flushing.
21 #define pr_fmt(fmt) "software IO TLB: " fmt
24 #include <linux/dma-direct.h>
25 #include <linux/dma-map-ops.h>
48 #include <linux/iommu-helper.h>
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/OK3568_Linux_fs/kernel/arch/powerpc/mm/
H A Dhugetlbpage.c2 * PPC Huge TLB Page Support for Kernel.
7 * Based on the IA-32 version:
23 #include <asm/tlb.h>
26 #include <asm/pte-walk.h>
32 #define PTE_T_ORDER (__builtin_ffs(sizeof(pte_basic_t)) - \
41 return __find_linux_pte(mm->pgd, addr, NULL, NULL); in huge_pte_offset()
50 int i; in __hugepte_alloc() local
55 num_hugepd = 1 << (pshift - pdshift); in __hugepte_alloc()
57 cachep = PGT_CACHE(pdshift - pshift); in __hugepte_alloc()
63 return -ENOMEM; in __hugepte_alloc()
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/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dtlb.c2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
21 void invalidate_tlb(u8 tlb) in invalidate_tlb() argument
23 if (tlb == 0) in invalidate_tlb()
25 if (tlb == 1) in invalidate_tlb()
31 int i; in init_tlbs() local
33 for (i = 0; i < num_tlb_entries; i++) { in init_tlbs()
34 write_tlb(tlb_table[i].mas0, in init_tlbs()
35 tlb_table[i].mas1, in init_tlbs()
36 tlb_table[i].mas2, in init_tlbs()
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/OK3568_Linux_fs/u-boot/doc/
H A DREADME.mpc85xx2 ----------------------
7 - MSR[DE] must be set
8 - A valid opcode must be fetchable, through the MMU, from the debug
11 To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
12 immediately on entry and keeps it set. It also uses a temporary TLB to keep a
15 where U-Boot currently executes from.
21 ----------------
26 ----------------------------------------------
40 TLB Entries during u-boot execution
41 -----------------------------------
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H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
9 - 8-stage pipeline.
10 - Dynamic branch prediction.
11 - 32/64/128/256 BTB.
12 - Return address stack (RAS).
13 - Vector interrupts for internal/external.
15 - 3 HW-level nested interruptions.
16 - User and super-user mode support.
17 - Memory-mapped I/O.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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/OK3568_Linux_fs/kernel/arch/powerpc/mm/book3s64/
H A Dhash_tlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * TLB and MMU hash table.
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
25 #include <asm/tlb.h>
27 #include <asm/pte-walk.h>
49 int i, offset; in hpte_need_flush() local
51 i = batch->index; in hpte_need_flush()
54 * Get page size (maybe move back to caller). in hpte_need_flush()
57 * for SPEs, we obtain the page size from the slice, which thus in hpte_need_flush()
64 /* Mask the address for the correct page size */ in hpte_need_flush()
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H A Dhash_native.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #include <asm/tlb.h>
27 #include <asm/ppc-opcode.h>
28 #include <asm/feature-fixups.h>
30 #include <misc/cxl-base.h>
57 * i.e., r=1 and is=01 or is=10 or is=11
71 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r) in tlbiel_hash_set_isa300()
107 * * PRS=1, R=0, and RIC!=2 (The only process-scoped in tlbiel_all_isa300()
113 * Then flush the sets of the TLB proper. Hash mode uses in tlbiel_all_isa300()
114 * partition scoped TLB translations, which may be flushed in tlbiel_all_isa300()
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/OK3568_Linux_fs/kernel/drivers/parisc/
H A Dccio-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
5 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
9 ** (c) Copyright 2000 Hewlett-Packard Company
15 ** the I/O MMU - basically what x86 does.
17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
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/OK3568_Linux_fs/kernel/include/asm-generic/
H A Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather
51 * Finish in particular will issue a (final) TLB invalidate and free
54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
59 * - tlb_remove_table()
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/OK3568_Linux_fs/kernel/Documentation/core-api/
H A Dcachetlb.rst2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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/OK3568_Linux_fs/kernel/arch/nios2/kernel/
H A Dcpuinfo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
41 if (!of_property_read_bool(cpu, "altr,has-initda")) in setup_cpuinfo()
43 "hardware system to have more than 4-byte line data " in setup_cpuinfo()
46 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); in setup_cpuinfo()
54 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); in setup_cpuinfo()
55 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); in setup_cpuinfo()
56 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); in setup_cpuinfo()
57 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); in setup_cpuinfo()
58 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); in setup_cpuinfo()
59 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); in setup_cpuinfo()
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/OK3568_Linux_fs/kernel/arch/powerpc/mm/nohash/
H A D44x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * -- paulus
11 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
27 #include <asm/code-patching.h>
31 /* Used by the 44x TLB replacement exception handler.
35 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
42 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
45 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
52 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
56 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
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H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains the routines for TLB flushing.
6 * this does -not- include 603 however which shares the implementation with
9 * -- BenH
15 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
39 #include <asm/tlb.h>
40 #include <asm/code-patching.h>
48 * This struct lists the sw-supported page sizes. The hardawre MMU may support
147 /* The variables below are currently only used on 64-bit Book3E
153 int mmu_linear_psize; /* Page size used for the linear mapping */
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/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dmmu.h28 unsigned long w:1; /* Write-thru cache mode */
29 unsigned long i:1; /* Cache inhibited */ member
44 unsigned long t:1; /* Normal or I/O type */
47 unsigned long n:1; /* No-execute */
57 unsigned long i:1; /* Cache inhibit */ member
71 unsigned long bl:11; /* Block size mask */
80 unsigned long bl:6; /* Block size mask */
90 unsigned long w:1; /* Write-thru cache */
91 unsigned long i:1; /* Cache inhibit */ member
109 * Simulated two-level MMU. This structure is used by the kernel
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/OK3568_Linux_fs/kernel/arch/parisc/include/uapi/asm/
H A Dpdc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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/OK3568_Linux_fs/kernel/arch/parisc/kernel/
H A Dcache.c6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10 * Cache and TLB management
42 /* On some machines (i.e., ones with the Merced bus), there can be
44 * by software. We need a spinlock around all TLB flushes to ensure
99 test_bit(PG_dcache_dirty, &page->flags)) { in __update_cache()
101 clear_bit(PG_dcache_dirty, &page->flags); in __update_cache()
111 seq_printf(m, "I-cache\t\t: %ld KB\n", in show_cache_info()
114 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop); in show_cache_info()
115 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n", in show_cache_info()
118 (cache_info.dc_conf.cc_sh ? ", shared I/D":""), in show_cache_info()
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/OK3568_Linux_fs/kernel/arch/microblaze/include/asm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
12 # include <asm-generic/mmu.h>
30 unsigned long w:1; /* Write-thru cache mode */
31 unsigned long i:1; /* Cache inhibited */ member
46 unsigned long t:1; /* Normal or I/O type */
49 unsigned long n:1; /* No-execute */
54 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
55 extern void _tlbia(void); /* invalidate all TLB entries */
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/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/nohash/32/
H A Dpte-44x.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Because of the 3 word TLB entries to support 36-bit addressing,
11 * are easily loaded during exception processing. I decided to
14 * in as sensibly as they can be in the area below a 4KB page size
16 * ERPN fields in the TLB. -Matt
19 * easier to move into the TLB from the PTE. -BenH.
21 * Note that these bits preclude future use of a page size
25 * PPC 440 core has following TLB attribute fields;
29 * RPN................................. - - - - - - ERPN.......
33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
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/OK3568_Linux_fs/kernel/arch/alpha/kernel/
H A Dpci_iommu.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
43 return (paddr >> (PAGE_SHIFT-1)) | 1; in mk_iommu_pte()
67 /* Note that the TLB lookup logic uses bitwise concatenation, in iommu_arena_new_node()
69 the size of the window. Retain the align parameter so that in iommu_arena_new_node()
70 particular systems can over-align the arena. */ in iommu_arena_new_node()
80 " falling back to system-wide allocation\n", in iommu_arena_new_node()
88 arena->ptes = memblock_alloc_node(sizeof(*arena), align, nid); in iommu_arena_new_node()
89 if (!NODE_DATA(nid) || !arena->ptes) { in iommu_arena_new_node()
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/OK3568_Linux_fs/u-boot/arch/nds32/cpu/n1213/
H A Dstart.S2 * Andesboot - Startup Code for Whitiger core
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm-offsets.h>
24 #define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
25 #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
26 #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
29 #define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
45 #define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
46 #define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
74 * 1.1 reset - start of u-boot
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/OK3568_Linux_fs/kernel/arch/mips/netlogic/xlp/
H A Dsetup.c2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
47 #include <asm/netlogic/xlp-hal/iomap.h>
48 #include <asm/netlogic/xlp-hal/xlp.h>
49 #include <asm/netlogic/xlp-hal/sys.h>
58 uint64_t sysbase = nlm_get_node(0)->sysbase; in nlm_linux_exit()
74 memblock_remove(mem->base + mem->size - pref_backup, in nlm_fixup_mem()
82 int i, n; in xlp_init_mem_from_bars() local
84 n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map)); /* -1 : all nodes */ in xlp_init_mem_from_bars()
85 for (i = 0; i < n; i += 2) { in xlp_init_mem_from_bars()
86 /* exclude 0x1000_0000-0x2000_0000, u-boot device */ in xlp_init_mem_from_bars()
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