1*4882a593SmuzhiyunN1213 is a configurable hard/soft core of NDS32's N12 CPU family. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunFeatures 4*4882a593Smuzhiyun======== 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunCPU Core 7*4882a593Smuzhiyun - 16-/32-bit mixable instruction format. 8*4882a593Smuzhiyun - 32 general-purpose 32-bit registers. 9*4882a593Smuzhiyun - 8-stage pipeline. 10*4882a593Smuzhiyun - Dynamic branch prediction. 11*4882a593Smuzhiyun - 32/64/128/256 BTB. 12*4882a593Smuzhiyun - Return address stack (RAS). 13*4882a593Smuzhiyun - Vector interrupts for internal/external. 14*4882a593Smuzhiyun interrupt controller with 6 hardware interrupt signals. 15*4882a593Smuzhiyun - 3 HW-level nested interruptions. 16*4882a593Smuzhiyun - User and super-user mode support. 17*4882a593Smuzhiyun - Memory-mapped I/O. 18*4882a593Smuzhiyun - Address space up to 4GB. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunMemory Management Unit 21*4882a593Smuzhiyun - TLB 22*4882a593Smuzhiyun - 4/8-entry fully associative iTLB/dTLB. 23*4882a593Smuzhiyun - 32/64/128-entry 4-way set-associati.ve main TLB. 24*4882a593Smuzhiyun - TLB locking support 25*4882a593Smuzhiyun - Optional hardware page table walker. 26*4882a593Smuzhiyun - Two groups of page size support. 27*4882a593Smuzhiyun - 4KB & 1MB. 28*4882a593Smuzhiyun - 8KB & 1MB. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunMemory Subsystem 31*4882a593Smuzhiyun - I & D cache. 32*4882a593Smuzhiyun - Virtually indexed and physically tagged. 33*4882a593Smuzhiyun - Cache size: 8KB/16KB/32KB/64KB. 34*4882a593Smuzhiyun - Cache line size: 16B/32B. 35*4882a593Smuzhiyun - Set associativity: 2-way, 4-way or direct-mapped. 36*4882a593Smuzhiyun - Cache locking support. 37*4882a593Smuzhiyun - I & D local memory (LM). 38*4882a593Smuzhiyun - Size: 4KB to 1MB. 39*4882a593Smuzhiyun - Bank numbers: 1 or 2. 40*4882a593Smuzhiyun - Optional 1D/2D DMA engine. 41*4882a593Smuzhiyun - Internal or external to CPU core. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunBus Interface 44*4882a593Smuzhiyun - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports. 45*4882a593Smuzhiyun - Synchronous High speed memory port. 46*4882a593Smuzhiyun (HSMP): 0, 1 or 2 ports. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunDebug 49*4882a593Smuzhiyun - JTAG debug interface. 50*4882a593Smuzhiyun - Embedded debug module (EDM). 51*4882a593Smuzhiyun - Optional embedded program tracer interface. 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunMiscellaneous 54*4882a593Smuzhiyun - Programmable data endian control. 55*4882a593Smuzhiyun - Performance monitoring mechanism. 56