1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_POWERPC_NOHASH_32_PTE_44x_H 3*4882a593Smuzhiyun #define _ASM_POWERPC_NOHASH_32_PTE_44x_H 4*4882a593Smuzhiyun #ifdef __KERNEL__ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* 7*4882a593Smuzhiyun * Definitions for PPC440 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Because of the 3 word TLB entries to support 36-bit addressing, 10*4882a593Smuzhiyun * the attribute are difficult to map in such a fashion that they 11*4882a593Smuzhiyun * are easily loaded during exception processing. I decided to 12*4882a593Smuzhiyun * organize the entry so the ERPN is the only portion in the 13*4882a593Smuzhiyun * upper word of the PTE and the attribute bits below are packed 14*4882a593Smuzhiyun * in as sensibly as they can be in the area below a 4KB page size 15*4882a593Smuzhiyun * oriented RPN. This at least makes it easy to load the RPN and 16*4882a593Smuzhiyun * ERPN fields in the TLB. -Matt 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * This isn't entirely true anymore, at least some bits are now 19*4882a593Smuzhiyun * easier to move into the TLB from the PTE. -BenH. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * Note that these bits preclude future use of a page size 22*4882a593Smuzhiyun * less than 4KB. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * PPC 440 core has following TLB attribute fields; 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * TLB1: 28*4882a593Smuzhiyun * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 29*4882a593Smuzhiyun * RPN................................. - - - - - - ERPN....... 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * TLB2: 32*4882a593Smuzhiyun * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33*4882a593Smuzhiyun * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional 36*4882a593Smuzhiyun * TLB2 storage attribute fields. Those are: 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * TLB2: 39*4882a593Smuzhiyun * 0...10 11 12 13 14 15 16...31 40*4882a593Smuzhiyun * no change WL1 IL1I IL1D IL2I IL2D no change 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * There are some constrains and options, to decide mapping software bits 43*4882a593Smuzhiyun * into TLB entry. 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * - PRESENT *must* be in the bottom three bits because swap cache 46*4882a593Smuzhiyun * entries use the top 29 bits for TLB2. 47*4882a593Smuzhiyun * 48*4882a593Smuzhiyun * - CACHE COHERENT bit (M) has no effect on original PPC440 cores, 49*4882a593Smuzhiyun * because it doesn't support SMP. However, some later 460 variants 50*4882a593Smuzhiyun * have -some- form of SMP support and so I keep the bit there for 51*4882a593Smuzhiyun * future use 52*4882a593Smuzhiyun * 53*4882a593Smuzhiyun * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used 54*4882a593Smuzhiyun * for memory protection related functions (see PTE structure in 55*4882a593Smuzhiyun * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the 56*4882a593Smuzhiyun * above bits. Note that the bit values are CPU specific, not architecture 57*4882a593Smuzhiyun * specific. 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * The kernel PTE entry holds an arch-dependent swp_entry structure under 60*4882a593Smuzhiyun * certain situations. In other words, in such situations some portion of 61*4882a593Smuzhiyun * the PTE bits are used as a swp_entry. In the PPC implementation, the 62*4882a593Smuzhiyun * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still 63*4882a593Smuzhiyun * hold protection values. That means the three protection bits are 64*4882a593Smuzhiyun * reserved for both PTE and SWAP entry at the most significant three 65*4882a593Smuzhiyun * LSBs. 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * There are three protection bits available for SWAP entry: 68*4882a593Smuzhiyun * _PAGE_PRESENT 69*4882a593Smuzhiyun * _PAGE_HASHPTE (if HW has) 70*4882a593Smuzhiyun * 71*4882a593Smuzhiyun * So those three bits have to be inside of 0-2nd LSB of PTE. 72*4882a593Smuzhiyun * 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ 76*4882a593Smuzhiyun #define _PAGE_RW 0x00000002 /* S: Write permission */ 77*4882a593Smuzhiyun #define _PAGE_EXEC 0x00000004 /* H: Execute permission */ 78*4882a593Smuzhiyun #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ 79*4882a593Smuzhiyun #define _PAGE_DIRTY 0x00000010 /* S: Page dirty */ 80*4882a593Smuzhiyun #define _PAGE_SPECIAL 0x00000020 /* S: Special page */ 81*4882a593Smuzhiyun #define _PAGE_USER 0x00000040 /* S: User page */ 82*4882a593Smuzhiyun #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ 83*4882a593Smuzhiyun #define _PAGE_GUARDED 0x00000100 /* H: G bit */ 84*4882a593Smuzhiyun #define _PAGE_COHERENT 0x00000200 /* H: M bit */ 85*4882a593Smuzhiyun #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ 86*4882a593Smuzhiyun #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* No page size encoding in the linux PTE */ 89*4882a593Smuzhiyun #define _PAGE_PSIZE 0 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define _PAGE_KERNEL_RO 0 92*4882a593Smuzhiyun #define _PAGE_KERNEL_ROX _PAGE_EXEC 93*4882a593Smuzhiyun #define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW) 94*4882a593Smuzhiyun #define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* TODO: Add large page lowmem mapping support */ 97*4882a593Smuzhiyun #define _PMD_PRESENT 0 98*4882a593Smuzhiyun #define _PMD_PRESENT_MASK (PAGE_MASK) 99*4882a593Smuzhiyun #define _PMD_BAD (~PAGE_MASK) 100*4882a593Smuzhiyun #define _PMD_USER 0 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* ERPN in a PTE never gets cleared, ignore it */ 103*4882a593Smuzhiyun #define _PTE_NONE_MASK 0xffffffff00000000ULL 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* 106*4882a593Smuzhiyun * We define 2 sets of base prot bits, one for basic pages (ie, 107*4882a593Smuzhiyun * cacheable kernel and user pages) and one for non cacheable 108*4882a593Smuzhiyun * pages. We always set _PAGE_COHERENT when SMP is enabled or 109*4882a593Smuzhiyun * the processor might need it for DMA coherency. 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 112*4882a593Smuzhiyun #if defined(CONFIG_SMP) 113*4882a593Smuzhiyun #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 114*4882a593Smuzhiyun #else 115*4882a593Smuzhiyun #define _PAGE_BASE (_PAGE_BASE_NC) 116*4882a593Smuzhiyun #endif 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Permission masks used to generate the __P and __S table */ 119*4882a593Smuzhiyun #define PAGE_NONE __pgprot(_PAGE_BASE) 120*4882a593Smuzhiyun #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 121*4882a593Smuzhiyun #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 122*4882a593Smuzhiyun #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 123*4882a593Smuzhiyun #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 124*4882a593Smuzhiyun #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 125*4882a593Smuzhiyun #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #endif /* __KERNEL__ */ 128*4882a593Smuzhiyun #endif /* _ASM_POWERPC_NOHASH_32_PTE_44x_H */ 129