1*4882a593SmuzhiyunExternal Debug Support 2*4882a593Smuzhiyun---------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunFreescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some 5*4882a593Smuzhiyunrestrictions on external debugging (JTAG). In particular, for the debugger to 6*4882a593Smuzhiyunbe able to receive control after a single step or breakpoint: 7*4882a593Smuzhiyun - MSR[DE] must be set 8*4882a593Smuzhiyun - A valid opcode must be fetchable, through the MMU, from the debug 9*4882a593Smuzhiyun exception vector (IVPR + IVOR15). 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunTo maximize the time during which this requirement is met, U-Boot sets MSR[DE] 12*4882a593Smuzhiyunimmediately on entry and keeps it set. It also uses a temporary TLB to keep a 13*4882a593Smuzhiyunmapping to a valid opcode at the debug exception vector, even if we normally 14*4882a593Smuzhiyundon't support exception vectors being used that early, and that's not the area 15*4882a593Smuzhiyunwhere U-Boot currently executes from. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunNote that there may still be some small windows where debugging will not work, 18*4882a593Smuzhiyunsuch as in between updating IVPR and IVOR15. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunConfig Switches: 21*4882a593Smuzhiyun---------------- 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunPlease refer README section "MPC85xx External Debug Support" 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunMajor Config Switches during various boot Modes 26*4882a593Smuzhiyun---------------------------------------------- 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunNOR boot 29*4882a593Smuzhiyun !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) 30*4882a593SmuzhiyunNOR boot Secure 31*4882a593Smuzhiyun !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 32*4882a593SmuzhiyunRAMBOOT(SD, SPI & NAND boot) 33*4882a593Smuzhiyun defined(CONFIG_SYS_RAMBOOT) 34*4882a593SmuzhiyunRAMBOOT Secure (SD, SPI & NAND) 35*4882a593Smuzhiyun defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 36*4882a593SmuzhiyunNAND SPL BOOT 37*4882a593Smuzhiyun defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunTLB Entries during u-boot execution 41*4882a593Smuzhiyun----------------------------------- 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunNote: Sequence number is in order of execution 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunA) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun 1) TLB entry to overcome e500 v1/v2 debug restriction 48*4882a593Smuzhiyun Location : Label "_start_e500" 49*4882a593Smuzhiyun TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 50*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE 51*4882a593Smuzhiyun Properties : 256K, AS0, I, IPROT 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun 2) TLB entry for working in AS1 54*4882a593Smuzhiyun Location : Label "create_init_ram_area" 55*4882a593Smuzhiyun TLB Entry : 15 56*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE 57*4882a593Smuzhiyun Properties : 1M, AS1, I, G, IPROT 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun 3) TLB entry for the stack during AS1 60*4882a593Smuzhiyun Location : Lable "create_init_ram_area" 61*4882a593Smuzhiyun TLB Entry : 14 62*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR 63*4882a593Smuzhiyun Properties : 16K, AS1, IPROT 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 4) TLB entry for CCSRBAR during AS1 execution 66*4882a593Smuzhiyun Location : cpu_init_early_f 67*4882a593Smuzhiyun TLB Entry : 13 68*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR 69*4882a593Smuzhiyun Properties : 1M, AS1, I, G 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun 5) Invalidate unproctected TLB Entries 72*4882a593Smuzhiyun Location : cpu_init_early_f 73*4882a593Smuzhiyun Invalidated: 13 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun 6) Create TLB entries as per boards/freescale/<board>/tlb.c 76*4882a593Smuzhiyun Location : cpu_init_early_f --> init_tlbs() 77*4882a593Smuzhiyun Properties : ..., AS0, ... 78*4882a593Smuzhiyun Please note It can overwrites previous TLB Entries. 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun 7) Disable TLB Entries of AS1 81*4882a593Smuzhiyun Location : cpu_init_f --> disable_tlb() 82*4882a593Smuzhiyun Disable : 15, 14 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun 8) Update Flash's TLB entry 85*4882a593Smuzhiyun Location : Board_init_r 86*4882a593Smuzhiyun TLB entry : Search from TLB entries 87*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS 88*4882a593Smuzhiyun Properties : Board specific size, AS0, I, G, IPROT 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunB) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun 1) TLB entry to overcome e500 v1/v2 debug restriction 94*4882a593Smuzhiyun Location : Label "_start_e500" 95*4882a593Smuzhiyun TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 96*4882a593Smuzhiyun#if defined(CONFIG_SECURE_BOOT) 97*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW 98*4882a593Smuzhiyun Properties : 1M, AS1, I, G, IPROT 99*4882a593Smuzhiyun#else 100*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 101*4882a593Smuzhiyun Properties : 4M, AS0, I, G, IPROT 102*4882a593Smuzhiyun#endif 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun 2) TLB entry for working in AS1 105*4882a593Smuzhiyun Location : Label "create_init_ram_area" 106*4882a593Smuzhiyun TLB Entry : 15 107*4882a593Smuzhiyun#if defined(CONFIG_SECURE_BOOT) 108*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW 109*4882a593Smuzhiyun Properties : 1M, AS1, I, G, IPROT 110*4882a593Smuzhiyun#else 111*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 112*4882a593Smuzhiyun Properties : 4M, AS1, I, G, IPROT 113*4882a593Smuzhiyun#endif 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun 3) TLB entry for the stack during AS1 116*4882a593Smuzhiyun Location : Lable "create_init_ram_area" 117*4882a593Smuzhiyun TLB Entry : 14 118*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR 119*4882a593Smuzhiyun Properties : 16K, AS1, IPROT 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun 4) TLB entry for CCSRBAR during AS1 execution 122*4882a593Smuzhiyun Location : cpu_init_early_f 123*4882a593Smuzhiyun TLB Entry : 13 124*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR 125*4882a593Smuzhiyun Properties : 1M, AS1, I, G 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 128*4882a593Smuzhiyun Location : cpu_init_early_f 129*4882a593Smuzhiyun TLB Entry : 9 130*4882a593Smuzhiyun EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR 131*4882a593Smuzhiyun Properties : 1M, AS1, I 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr 134*4882a593Smuzhiyun Location : cpu_init_early_f --> setup_ifc 135*4882a593Smuzhiyun TLB Entry : Get Flash TLB 136*4882a593Smuzhiyun EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys 137*4882a593Smuzhiyun Properties : 4M, AS1, I, G, IPROT 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction 140*4882a593Smuzhiyun Location : cpu_init_early_f --> setup_ifc 141*4882a593Smuzhiyun TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 142*4882a593Smuzhiyun EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys 143*4882a593Smuzhiyun Properties : 4M, AS0, I, G, IPROT 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun 8) Invalidate unproctected TLB Entries 146*4882a593Smuzhiyun Location : cpu_init_early_f 147*4882a593Smuzhiyun Invalidated: 13, 9 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun 9) Create TLB entries as per boards/freescale/<board>/tlb.c 150*4882a593Smuzhiyun Location : cpu_init_early_f --> init_tlbs() 151*4882a593Smuzhiyun Properties : ..., AS0, ... 152*4882a593Smuzhiyun Note: It can overwrites previous TLB Entries 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun 10) Disable TLB Entries of AS1 155*4882a593Smuzhiyun Location : cpu_init_f --> disable_tlb() 156*4882a593Smuzhiyun Disable : 15, 14 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun 11) Create DDR's TLB entriy 159*4882a593Smuzhiyun Location : Board_init_f -> dram_init 160*4882a593Smuzhiyun TLB entry : Search free TLB entry 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun 12) Update Flash's TLB entry 163*4882a593Smuzhiyun Location : Board_init_r 164*4882a593Smuzhiyun TLB entry : Search from TLB entries 165*4882a593Smuzhiyun EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS 166*4882a593Smuzhiyun Properties : Board specific size, AS0, I, G, IPROT 167