1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 4*4882a593Smuzhiyun * Copyright (C) 2008-2009 PetaLogix 5*4882a593Smuzhiyun * Copyright (C) 2006 Atmark Techno, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_MICROBLAZE_MMU_H 9*4882a593Smuzhiyun #define _ASM_MICROBLAZE_MMU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun # ifndef CONFIG_MMU 12*4882a593Smuzhiyun # include <asm-generic/mmu.h> 13*4882a593Smuzhiyun # else /* CONFIG_MMU */ 14*4882a593Smuzhiyun # ifdef __KERNEL__ 15*4882a593Smuzhiyun # ifndef __ASSEMBLY__ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Default "unsigned long" context */ 18*4882a593Smuzhiyun typedef unsigned long mm_context_t; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Hardware Page Table Entry */ 21*4882a593Smuzhiyun typedef struct _PTE { 22*4882a593Smuzhiyun unsigned long v:1; /* Entry is valid */ 23*4882a593Smuzhiyun unsigned long vsid:24; /* Virtual segment identifier */ 24*4882a593Smuzhiyun unsigned long h:1; /* Hash algorithm indicator */ 25*4882a593Smuzhiyun unsigned long api:6; /* Abbreviated page index */ 26*4882a593Smuzhiyun unsigned long rpn:20; /* Real (physical) page number */ 27*4882a593Smuzhiyun unsigned long :3; /* Unused */ 28*4882a593Smuzhiyun unsigned long r:1; /* Referenced */ 29*4882a593Smuzhiyun unsigned long c:1; /* Changed */ 30*4882a593Smuzhiyun unsigned long w:1; /* Write-thru cache mode */ 31*4882a593Smuzhiyun unsigned long i:1; /* Cache inhibited */ 32*4882a593Smuzhiyun unsigned long m:1; /* Memory coherence */ 33*4882a593Smuzhiyun unsigned long g:1; /* Guarded */ 34*4882a593Smuzhiyun unsigned long :1; /* Unused */ 35*4882a593Smuzhiyun unsigned long pp:2; /* Page protection */ 36*4882a593Smuzhiyun } PTE; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Values for PP (assumes Ks=0, Kp=1) */ 39*4882a593Smuzhiyun # define PP_RWXX 0 /* Supervisor read/write, User none */ 40*4882a593Smuzhiyun # define PP_RWRX 1 /* Supervisor read/write, User read */ 41*4882a593Smuzhiyun # define PP_RWRW 2 /* Supervisor read/write, User read/write */ 42*4882a593Smuzhiyun # define PP_RXRX 3 /* Supervisor read, User read */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Segment Register */ 45*4882a593Smuzhiyun typedef struct _SEGREG { 46*4882a593Smuzhiyun unsigned long t:1; /* Normal or I/O type */ 47*4882a593Smuzhiyun unsigned long ks:1; /* Supervisor 'key' (normally 0) */ 48*4882a593Smuzhiyun unsigned long kp:1; /* User 'key' (normally 1) */ 49*4882a593Smuzhiyun unsigned long n:1; /* No-execute */ 50*4882a593Smuzhiyun unsigned long :4; /* Unused */ 51*4882a593Smuzhiyun unsigned long vsid:24; /* Virtual Segment Identifier */ 52*4882a593Smuzhiyun } SEGREG; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ 55*4882a593Smuzhiyun extern void _tlbia(void); /* invalidate all TLB entries */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB 59*4882a593Smuzhiyun * mapping has to increase tlb_skip size. 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun extern u32 tlb_skip; 62*4882a593Smuzhiyun # endif /* __ASSEMBLY__ */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 66*4882a593Smuzhiyun * instruction and data sides share a unified, 64-entry, semi-associative 67*4882a593Smuzhiyun * TLB which is maintained totally under software control. In addition, the 68*4882a593Smuzhiyun * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative 69*4882a593Smuzhiyun * TLB which serves as a first level to the shared TLB. These two TLBs are 70*4882a593Smuzhiyun * known as the UTLB and ITLB, respectively. 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun # define MICROBLAZE_TLB_SIZE 64 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* For cases when you want to skip some TLB entries */ 76*4882a593Smuzhiyun # define MICROBLAZE_TLB_SKIP 0 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Use the last TLB for temporary access to LMB */ 79*4882a593Smuzhiyun # define MICROBLAZE_LMB_TLB_ID 63 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * TLB entries are defined by a "high" tag portion and a "low" data 83*4882a593Smuzhiyun * portion. The data portion is 32-bits. 84*4882a593Smuzhiyun * 85*4882a593Smuzhiyun * TLB entries are managed entirely under software control by reading, 86*4882a593Smuzhiyun * writing, and searching using the MTS and MFS instructions. 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun # define TLB_LO 1 90*4882a593Smuzhiyun # define TLB_HI 0 91*4882a593Smuzhiyun # define TLB_DATA TLB_LO 92*4882a593Smuzhiyun # define TLB_TAG TLB_HI 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Tag portion */ 95*4882a593Smuzhiyun # define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ 96*4882a593Smuzhiyun # define TLB_PAGESZ_MASK 0x00000380 97*4882a593Smuzhiyun # define TLB_PAGESZ(x) (((x) & 0x7) << 7) 98*4882a593Smuzhiyun # define PAGESZ_1K 0 99*4882a593Smuzhiyun # define PAGESZ_4K 1 100*4882a593Smuzhiyun # define PAGESZ_16K 2 101*4882a593Smuzhiyun # define PAGESZ_64K 3 102*4882a593Smuzhiyun # define PAGESZ_256K 4 103*4882a593Smuzhiyun # define PAGESZ_1M 5 104*4882a593Smuzhiyun # define PAGESZ_4M 6 105*4882a593Smuzhiyun # define PAGESZ_16M 7 106*4882a593Smuzhiyun # define TLB_VALID 0x00000040 /* Entry is valid */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* Data portion */ 109*4882a593Smuzhiyun # define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ 110*4882a593Smuzhiyun # define TLB_PERM_MASK 0x00000300 111*4882a593Smuzhiyun # define TLB_EX 0x00000200 /* Instruction execution allowed */ 112*4882a593Smuzhiyun # define TLB_WR 0x00000100 /* Writes permitted */ 113*4882a593Smuzhiyun # define TLB_ZSEL_MASK 0x000000F0 114*4882a593Smuzhiyun # define TLB_ZSEL(x) (((x) & 0xF) << 4) 115*4882a593Smuzhiyun # define TLB_ATTR_MASK 0x0000000F 116*4882a593Smuzhiyun # define TLB_W 0x00000008 /* Caching is write-through */ 117*4882a593Smuzhiyun # define TLB_I 0x00000004 /* Caching is inhibited */ 118*4882a593Smuzhiyun # define TLB_M 0x00000002 /* Memory is coherent */ 119*4882a593Smuzhiyun # define TLB_G 0x00000001 /* Memory is guarded from prefetch */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun # endif /* __KERNEL__ */ 122*4882a593Smuzhiyun # endif /* CONFIG_MMU */ 123*4882a593Smuzhiyun #endif /* _ASM_MICROBLAZE_MMU_H */ 124