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/OK3568_Linux_fs/kernel/sound/soc/atmel/
H A Datmel-pcm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * at91-pcm.h - ALSA PCM interface for the Atmel AT91 SoC.
10 * Based on at91-pcm. by:
14 * Based on pxa2xx-pcm.c by:
24 #include <linux/atmel-ssc.h>
40 u32 ssc_enable; /* SSC recv/trans enable */
41 u32 ssc_disable; /* SSC recv/trans disable */
42 u32 ssc_error; /* SSC error conditions */
43 u32 ssc_endx; /* SSC ENDTX or ENDRX */
44 u32 ssc_endbuf; /* SSC TXBUFE or RXBUFF */
[all …]
H A Datmel_ssc_dai.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
11 * Based on at91-ssc.c by
25 #include <linux/atmel-ssc.h>
32 #include "atmel-pcm.h"
39 * SSC PDC registers required by the PCM DMA engine.
56 * SSC & PDC status bits for transmit and receive.
136 * SSC interrupt handler. Passes PDC interrupts to the DMA
147 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) in atmel_ssc_interrupt()
148 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); in atmel_ssc_interrupt()
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-pci-gli.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
16 #include "sdhci-pci.h"
218 /* enable tuning parameters control */ in gli_set_9750()
275 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
288 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
290 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
291 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
295 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
298 return -EAGAIN; in __sdhci_execute_tuning_9750()
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/OK3568_Linux_fs/kernel/include/linux/
H A Datmel-ssc.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 void ssc_free(struct ssc_device *ssc);
30 /* SSC register offsets */
32 /* SSC Control Register */
45 /* SSC Clock Mode Register */
50 /* SSC Receive Clock Mode Register */
69 /* SSC Receive Frame Mode Register */
92 /* SSC Transmit Clock Mode Register */
109 /* SSC Transmit Frame Mode Register */
134 /* SSC Receive Hold Register */
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/OK3568_Linux_fs/kernel/drivers/scsi/mvsas/
H A Dmv_94xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
45 MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
61 MVS_INT_MASK = 0x154, /* Central int enable */
66 MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
72 /* ports 1-3 follow after this */
75 /* ports 5-7 follow after this */
77 MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
79 /* ports 1-3 follow after this */
81 /* ports 5-7 follow after this */
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/isci/
H A Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
80 * This field specifies the NOTIFY (ENABLE SPIN UP) primitive
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
229 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
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/OK3568_Linux_fs/kernel/sound/spi/
H A Dat73c213.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for AT73C213 16-bit stereo DAC connected to Atmel SSC
5 * Copyright (C) 2006-2007 Atmel Norway
14 #include <linux/dma-mapping.h>
27 #include <linux/atmel-ssc.h>
41 0x00, /* 00 - CTRL */
42 0x05, /* 01 - LLIG */
43 0x05, /* 02 - RLIG */
44 0x08, /* 03 - LPMG */
45 0x08, /* 04 - RPMG */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/panel/
H A Dpanel-maxim-max96772.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <uapi/linux/media-bus-format.h>
34 bool ssc; member
38 int (*enable)(struct max96772_panel *p); member
56 bool ssc; member
62 ret = regmap_write(p->regmap.serializer, reg, val); \
69 ret = regmap_read(p->regmap.serializer, reg, val); \
76 ret = regmap_write(p->regmap.deserializer, reg, val); \
83 ret = regmap_read(p->regmap.deserializer, reg, val); \
153 const struct drm_display_mode *mode = &p->mode; in max96772_prepare()
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/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
26 /* SSC registers */
34 /* SSC Control */
49 /* SSC Interrupt Enable */
55 /* SSC SPI Controller */
60 /* SSC SPI current transaction */
75 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
78 count = spi_st->words_remaining; in ssc_write_tx_fifo()
81 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
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/OK3568_Linux_fs/kernel/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
303 u32 rate, bool ssc);
308 u32 rate, bool ssc);
365 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
367 writew(val, ctx->base + offset); in cdns_regmap_write()
375 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
377 *val = readw(ctx->base + offset); in cdns_regmap_read()
387 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
398 *val = readl(ctx->base + offset); in cdns_regmap_dptx_read()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dbrcm-sata-phy.txt4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
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/OK3568_Linux_fs/u-boot/include/
H A Dgeneric-phy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
49 * Pre-emphasis levels, as specified by DisplayPort specification, to be
57 * @ssc:
59 * Flag indicating, whether or not to enable spread-spectrum clocking.
62 u8 ssc : 1; member
67 * Flag indicating, whether or not reconfigure link rate and SSC to
86 * and pre-emphasis to requested values. Only lanes specified
/OK3568_Linux_fs/kernel/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
59 * @ssc:
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
64 u8 ssc : 1; member
69 * Flag indicating, whether or not reconfigure link rate and SSC to
88 * and pre-emphasis to requested values. Only lanes specified
/OK3568_Linux_fs/kernel/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
61 /* PLL SSC step size offsets */
70 /* SSC step size parameters */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
174 * @steps: number of steps of SSC (Spread Spectrum Clock)
185 * struct xpsgtr_phy - representation of a lane
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Danalogix_dp.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch-rockchip/clock.h>
32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
37 * @ssc: check if SSC is supported by source
44 bool ssc; member
52 bool enable) in analogix_dp_enable_rx_to_enhanced_mode() argument
58 if (enable) in analogix_dp_enable_rx_to_enhanced_mode()
100 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
102 dp->link_train.lt_state = CLOCK_RECOVERY; in analogix_dp_link_start()
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/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <dt-bindings/phy/phy.h>
13 #include <generic-phy.h>
18 #include <reset-uclass.h>
29 u16 enable; member
91 tmp = en ? reg->enable : reg->disable; in param_write()
92 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
93 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
95 return regmap_write(base, reg->offset, val); in param_write()
102 if (priv->cfg->combphy_cfg) { in rockchip_combphy_pcie_init()
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/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* SSC registers */
47 /* SSC Control */
62 /* SSC Interrupt Enable */
76 /* SSC Status */
93 /* SSC I2C Control */
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
109 /* SSC Clear bit operation */
116 /* SSC Clock Prescaler */
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/OK3568_Linux_fs/kernel/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <dt-bindings/phy/phy.h>
170 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
172 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
210 bool ssc; member
237 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
366 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
377 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
378 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
390 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
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/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <dt-bindings/phy/phy.h>
30 u16 enable; member
98 ret = regmap_read(base, reg->offset, &orig); in param_read()
102 mask = GENMASK(reg->bitend, reg->bitstart); in param_read()
103 tmp = (orig & mask) >> reg->bitstart; in param_read()
113 tmp = en ? reg->enable : reg->disable; in param_write()
114 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
115 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
117 return regmap_write(base, reg->offset, val); in param_write()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
18 - brcm,bcm7278-pcie # Broadcom 7278 Arm
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
34 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
278 bool ssc; member
294 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
302 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
305 return log2_in - 15; in brcm_pcie_encode_ibar_size()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { in analogix_dp_write()
25 readl(dp->reg_base); in analogix_dp_write()
26 writel(val, dp->reg_base + reg); in analogix_dp_write()
29 writel(val, dp->reg_base + reg); in analogix_dp_write()
34 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) in analogix_dp_read()
35 readl(dp->reg_base + reg); in analogix_dp_read()
37 return readl(dp->reg_base + reg); in analogix_dp_read()
40 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) in analogix_dp_enable_video_mute() argument
44 if (enable) { in analogix_dp_enable_video_mute()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
54 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
60 * @ssc: check if SSC is supported by source
70 bool ssc; member
109 if (!field->valid) in rockchip_grf_field_write()
112 mask = GENMASK(field->msb, field->lsb); in rockchip_grf_field_write()
113 val <<= field->lsb; in rockchip_grf_field_write()
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/OK3568_Linux_fs/kernel/drivers/staging/mt7621-pci-phy/
H A Dpci-mt7621-phy.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
84 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
106 regmap_read(phy->regmap, reg, &val); in phy_read()
113 regmap_write(phy->regmap, reg, val); in phy_write()
131 if (phy->has_dual_port) { in mt7621_bypass_pipe_rst()
141 struct device *dev = phy->dev; in mt7621_set_phy_for_ssc()
147 /* Set PCIe Port PHY to disable SSC */ in mt7621_set_phy_for_ssc()
157 if (phy->has_dual_port) { in mt7621_set_phy_for_ssc()
163 /* Set Pre-divider ratio (for host mode) */ in mt7621_set_phy_for_ssc()
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