1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip PIPE USB3.0 PCIE SATA combphy driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/phy/phy.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <dt-bindings/phy/phy.h>
20
21 #define BIT_WRITEABLE_SHIFT 16
22
23 struct rockchip_combphy_priv;
24
25 struct combphy_reg {
26 u32 offset;
27 u16 bitend;
28 u16 bitstart;
29 u16 disable;
30 u16 enable;
31 };
32
33 struct rockchip_combphy_grfcfg {
34 struct combphy_reg pcie_mode_set;
35 struct combphy_reg usb_mode_set;
36 struct combphy_reg sgmii_mode_set;
37 struct combphy_reg qsgmii_mode_set;
38 struct combphy_reg pipe_rxterm_set;
39 struct combphy_reg pipe_txelec_set;
40 struct combphy_reg pipe_txcomp_set;
41 struct combphy_reg pipe_clk_24m;
42 struct combphy_reg pipe_clk_25m;
43 struct combphy_reg pipe_clk_100m;
44 struct combphy_reg pipe_phymode_sel;
45 struct combphy_reg pipe_rate_sel;
46 struct combphy_reg pipe_rxterm_sel;
47 struct combphy_reg pipe_txelec_sel;
48 struct combphy_reg pipe_txcomp_sel;
49 struct combphy_reg pipe_clk_ext;
50 struct combphy_reg pipe_sel_usb;
51 struct combphy_reg pipe_sel_qsgmii;
52 struct combphy_reg pipe_phy_status;
53 struct combphy_reg con0_for_pcie;
54 struct combphy_reg con1_for_pcie;
55 struct combphy_reg con2_for_pcie;
56 struct combphy_reg con3_for_pcie;
57 struct combphy_reg con0_for_sata;
58 struct combphy_reg con1_for_sata;
59 struct combphy_reg con2_for_sata;
60 struct combphy_reg con3_for_sata;
61 struct combphy_reg pipe_con0_for_sata;
62 struct combphy_reg pipe_con1_for_sata;
63 struct combphy_reg pipe_sgmii_mac_sel;
64 struct combphy_reg pipe_xpcs_phy_ready;
65 struct combphy_reg u3otg0_port_en;
66 struct combphy_reg u3otg1_port_en;
67 struct combphy_reg pipe_phy_grf_reset;
68 };
69
70 struct rockchip_combphy_cfg {
71 const int num_clks;
72 const struct clk_bulk_data *clks;
73 const struct rockchip_combphy_grfcfg *grfcfg;
74 bool force_det_out; /* Tx detect Rx errata */
75 int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
76 };
77
78 struct rockchip_combphy_priv {
79 u8 mode;
80 void __iomem *mmio;
81 int num_clks;
82 struct clk_bulk_data *clks;
83 struct device *dev;
84 struct regmap *pipe_grf;
85 struct regmap *phy_grf;
86 struct phy *phy;
87 struct reset_control *apb_rst;
88 struct reset_control *phy_rst;
89 const struct rockchip_combphy_cfg *cfg;
90 };
91
param_read(struct regmap * base,const struct combphy_reg * reg,u32 val)92 static inline bool param_read(struct regmap *base,
93 const struct combphy_reg *reg, u32 val)
94 {
95 int ret;
96 u32 mask, orig, tmp;
97
98 ret = regmap_read(base, reg->offset, &orig);
99 if (ret)
100 return false;
101
102 mask = GENMASK(reg->bitend, reg->bitstart);
103 tmp = (orig & mask) >> reg->bitstart;
104
105 return tmp == val;
106 }
107
param_write(struct regmap * base,const struct combphy_reg * reg,bool en)108 static int param_write(struct regmap *base,
109 const struct combphy_reg *reg, bool en)
110 {
111 u32 val, mask, tmp;
112
113 tmp = en ? reg->enable : reg->disable;
114 mask = GENMASK(reg->bitend, reg->bitstart);
115 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
116
117 return regmap_write(base, reg->offset, val);
118 }
119
rockchip_combphy_is_ready(struct rockchip_combphy_priv * priv)120 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
121 {
122 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
123 u32 mask, val;
124
125 mask = GENMASK(cfg->pipe_phy_status.bitend,
126 cfg->pipe_phy_status.bitstart);
127
128 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
129 val = (val & mask) >> cfg->pipe_phy_status.bitstart;
130
131 return val;
132 }
133
rockchip_combphy_pcie_init(struct rockchip_combphy_priv * priv)134 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
135 {
136 int ret = 0;
137 u32 val;
138
139 if (priv->cfg->combphy_cfg) {
140 ret = priv->cfg->combphy_cfg(priv);
141 if (ret) {
142 dev_err(priv->dev, "failed to init phy for pcie\n");
143 return ret;
144 }
145 }
146
147 if (priv->cfg->force_det_out) {
148 val = readl(priv->mmio + (0x19 << 2));
149 val |= BIT(5);
150 writel(val, priv->mmio + (0x19 << 2));
151 }
152
153 return ret;
154 }
155
rockchip_combphy_usb3_init(struct rockchip_combphy_priv * priv)156 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
157 {
158 const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
159 int ret = 0;
160
161 if (device_property_present(priv->dev, "rockchip,dis-u3otg0-port")) {
162 ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
163 false);
164 return ret;
165 } else if (device_property_present(priv->dev, "rockchip,dis-u3otg1-port")) {
166 ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
167 false);
168 return ret;
169 }
170
171 if (priv->cfg->combphy_cfg) {
172 ret = priv->cfg->combphy_cfg(priv);
173 if (ret) {
174 dev_err(priv->dev, "failed to init phy for usb3\n");
175 return ret;
176 }
177 }
178
179 return ret;
180 }
181
rockchip_combphy_sata_init(struct rockchip_combphy_priv * priv)182 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
183 {
184 int ret = 0;
185
186 if (priv->cfg->combphy_cfg) {
187 ret = priv->cfg->combphy_cfg(priv);
188 if (ret) {
189 dev_err(priv->dev, "failed to init phy for sata\n");
190 return ret;
191 }
192 }
193
194 return ret;
195 }
196
rockchip_combphy_sgmii_init(struct rockchip_combphy_priv * priv)197 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
198 {
199 int ret = 0;
200
201 if (priv->cfg->combphy_cfg) {
202 ret = priv->cfg->combphy_cfg(priv);
203 if (ret) {
204 dev_err(priv->dev, "failed to init phy for sgmii\n");
205 return ret;
206 }
207 }
208
209 return ret;
210 }
211
rockchip_combphy_set_mode(struct rockchip_combphy_priv * priv)212 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
213 {
214 switch (priv->mode) {
215 case PHY_TYPE_PCIE:
216 rockchip_combphy_pcie_init(priv);
217 break;
218 case PHY_TYPE_USB3:
219 rockchip_combphy_usb3_init(priv);
220 break;
221 case PHY_TYPE_SATA:
222 rockchip_combphy_sata_init(priv);
223 break;
224 case PHY_TYPE_SGMII:
225 case PHY_TYPE_QSGMII:
226 return rockchip_combphy_sgmii_init(priv);
227 default:
228 dev_err(priv->dev, "incompatible PHY type\n");
229 return -EINVAL;
230 }
231
232 return 0;
233 }
234
rockchip_combphy_init(struct phy * phy)235 static int rockchip_combphy_init(struct phy *phy)
236 {
237 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
238 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
239 u32 val;
240 int ret;
241
242 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
243 if (ret) {
244 dev_err(priv->dev, "failed to enable clks\n");
245 return ret;
246 }
247
248 ret = rockchip_combphy_set_mode(priv);
249 if (ret)
250 goto err_clk;
251
252 ret = reset_control_deassert(priv->phy_rst);
253 if (ret)
254 goto err_clk;
255
256 if (cfg->pipe_phy_grf_reset.enable)
257 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false);
258
259 if (priv->mode == PHY_TYPE_USB3) {
260 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
261 priv, val,
262 val == cfg->pipe_phy_status.enable,
263 10, 1000);
264 if (ret)
265 dev_warn(priv->dev, "wait phy status ready timeout\n");
266 }
267
268 return 0;
269
270 err_clk:
271 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
272
273 return ret;
274 }
275
rockchip_combphy_exit(struct phy * phy)276 static int rockchip_combphy_exit(struct phy *phy)
277 {
278 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
279 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
280
281 if (cfg->pipe_phy_grf_reset.enable)
282 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true);
283
284 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
285 reset_control_assert(priv->phy_rst);
286
287 return 0;
288 }
289
290 static const struct phy_ops rochchip_combphy_ops = {
291 .init = rockchip_combphy_init,
292 .exit = rockchip_combphy_exit,
293 .owner = THIS_MODULE,
294 };
295
rockchip_combphy_xlate(struct device * dev,struct of_phandle_args * args)296 static struct phy *rockchip_combphy_xlate(struct device *dev,
297 struct of_phandle_args *args)
298 {
299 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
300
301 if (args->args_count != 1) {
302 dev_err(dev, "invalid number of arguments\n");
303 return ERR_PTR(-EINVAL);
304 }
305
306 if (priv->mode != PHY_NONE && priv->mode != args->args[0])
307 dev_warn(dev, "phy type select %d overwriting type %d\n",
308 args->args[0], priv->mode);
309
310 priv->mode = args->args[0];
311
312 return priv->phy;
313 }
314
rockchip_combphy_parse_dt(struct device * dev,struct rockchip_combphy_priv * priv)315 static int rockchip_combphy_parse_dt(struct device *dev,
316 struct rockchip_combphy_priv *priv)
317 {
318 const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
319 int ret, mac_id;
320 u32 vals[4];
321
322 ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
323 if (ret == -EPROBE_DEFER)
324 return -EPROBE_DEFER;
325 if (ret)
326 priv->num_clks = 0;
327
328 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
329 "rockchip,pipe-grf");
330 if (IS_ERR(priv->pipe_grf)) {
331 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
332 return PTR_ERR(priv->pipe_grf);
333 }
334
335 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
336 "rockchip,pipe-phy-grf");
337 if (IS_ERR(priv->phy_grf)) {
338 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
339 return PTR_ERR(priv->phy_grf);
340 }
341
342 if (device_property_present(dev, "rockchip,dis-u3otg0-port"))
343 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
344 false);
345 else if (device_property_present(dev, "rockchip,dis-u3otg1-port"))
346 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
347 false);
348
349 if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) &&
350 (mac_id > 0))
351 param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
352 true);
353
354 if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
355 vals, ARRAY_SIZE(vals)))
356 regmap_write(priv->pipe_grf, vals[0],
357 (GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1]));
358
359 priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
360 if (IS_ERR(priv->apb_rst)) {
361 ret = PTR_ERR(priv->apb_rst);
362
363 if (ret != -EPROBE_DEFER)
364 dev_warn(dev, "failed to get apb reset\n");
365
366 return ret;
367 }
368
369 priv->phy_rst = devm_reset_control_get_optional(dev, "combphy");
370 if (IS_ERR(priv->phy_rst)) {
371 ret = PTR_ERR(priv->phy_rst);
372
373 if (ret != -EPROBE_DEFER)
374 dev_warn(dev, "failed to get phy reset\n");
375
376 return ret;
377 }
378
379 return reset_control_assert(priv->phy_rst);
380 }
381
rockchip_combphy_probe(struct platform_device * pdev)382 static int rockchip_combphy_probe(struct platform_device *pdev)
383 {
384 struct phy_provider *phy_provider;
385 struct device *dev = &pdev->dev;
386 struct rockchip_combphy_priv *priv;
387 const struct rockchip_combphy_cfg *phy_cfg;
388 struct resource *res;
389 int ret;
390
391 phy_cfg = of_device_get_match_data(dev);
392 if (!phy_cfg) {
393 dev_err(dev, "No OF match data provided\n");
394 return -EINVAL;
395 }
396
397 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
398 if (!priv)
399 return -ENOMEM;
400
401 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
402 priv->mmio = devm_ioremap_resource(dev, res);
403 if (IS_ERR(priv->mmio)) {
404 ret = PTR_ERR(priv->mmio);
405 return ret;
406 }
407
408 priv->num_clks = phy_cfg->num_clks;
409
410 priv->clks = devm_kmemdup(dev, phy_cfg->clks,
411 phy_cfg->num_clks * sizeof(struct clk_bulk_data),
412 GFP_KERNEL);
413
414 if (!priv->clks)
415 return -ENOMEM;
416
417 priv->dev = dev;
418 priv->mode = PHY_NONE;
419 priv->cfg = phy_cfg;
420
421 ret = rockchip_combphy_parse_dt(dev, priv);
422 if (ret)
423 return ret;
424
425 priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
426 if (IS_ERR(priv->phy)) {
427 dev_err(dev, "failed to create combphy\n");
428 return PTR_ERR(priv->phy);
429 }
430
431 dev_set_drvdata(dev, priv);
432 phy_set_drvdata(priv->phy, priv);
433
434 phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
435
436 return PTR_ERR_OR_ZERO(phy_provider);
437 }
438
rk3528_combphy_cfg(struct rockchip_combphy_priv * priv)439 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
440 {
441 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
442 struct clk *refclk = NULL;
443 unsigned long rate;
444 int i;
445 u32 val;
446
447 /* Configure PHY reference clock frequency */
448 for (i = 0; i < priv->num_clks; i++) {
449 if (!strncmp(priv->clks[i].id, "refclk", 6)) {
450 refclk = priv->clks[i].clk;
451 break;
452 }
453 }
454
455 if (!refclk) {
456 dev_err(priv->dev, "No refclk found\n");
457 return -EINVAL;
458 }
459
460 switch (priv->mode) {
461 case PHY_TYPE_PCIE:
462 /* Set SSC downward spread spectrum */
463 val = readl(priv->mmio + 0x18);
464 val &= ~GENMASK(5, 4);
465 val |= 0x01 << 4;
466 writel(val, priv->mmio + 0x18);
467
468 param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
469 param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
470 param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
471 param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
472 break;
473 case PHY_TYPE_USB3:
474 /* Set SSC downward spread spectrum */
475 val = readl(priv->mmio + 0x18);
476 val &= ~GENMASK(5, 4);
477 val |= 0x01 << 4;
478 writel(val, priv->mmio + 0x18);
479
480 /* Enable adaptive CTLE for USB3.0 Rx */
481 val = readl(priv->mmio + 0x200);
482 val &= ~GENMASK(17, 17);
483 val |= 0x01 << 17;
484 writel(val, priv->mmio + 0x200);
485
486 /* Set Rx squelch input filler bandwidth */
487 val = readl(priv->mmio + 0x20c);
488 val &= ~GENMASK(2, 0);
489 val |= 0x06;
490 writel(val, priv->mmio + 0x20c);
491
492 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
493 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
494 param_write(priv->phy_grf, &cfg->usb_mode_set, true);
495 break;
496 default:
497 dev_err(priv->dev, "incompatible PHY type\n");
498 return -EINVAL;
499 }
500
501 rate = clk_get_rate(refclk);
502
503 switch (rate) {
504 case 24000000:
505 param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
506 if (priv->mode == PHY_TYPE_USB3) {
507 /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
508 val = readl(priv->mmio + 0x100);
509 val &= ~GENMASK(10, 0);
510 val |= 0x17d;
511 writel(val, priv->mmio + 0x100);
512 } else if (priv->mode == PHY_TYPE_PCIE) {
513 /* tx_trim[14]=1, Enable the counting clock of the rterm detect */
514 val = readl(priv->mmio + 0x218);
515 val |= (1 << 14);
516 writel(val, priv->mmio + 0x218);
517 }
518 break;
519 case 100000000:
520 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
521 if (priv->mode == PHY_TYPE_PCIE) {
522 /* PLL KVCO tuning fine */
523 val = readl(priv->mmio + 0x18);
524 val &= ~(0x7 << 10);
525 val |= 0x2 << 10;
526 writel(val, priv->mmio + 0x18);
527
528 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */
529 val = 0x570804f0;
530 writel(val, priv->mmio + 0x108);
531 }
532 break;
533 default:
534 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
535 return -EINVAL;
536 }
537
538 return 0;
539 }
540
541 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
542 /* pipe-phy-grf */
543 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 },
544 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 },
545 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 },
546 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 },
547 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 },
548 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 },
549 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 },
550 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 },
551 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 },
552 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 },
553 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 },
554 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 },
555 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 },
556 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 },
557 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 },
558 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 },
559 /* pipe-grf */
560 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 },
561 };
562
563 static const struct clk_bulk_data rk3528_clks[] = {
564 { .id = "refclk" },
565 { .id = "apbclk" },
566 { .id = "pipe_clk" },
567 };
568
569 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
570 .num_clks = ARRAY_SIZE(rk3528_clks),
571 .clks = rk3528_clks,
572 .grfcfg = &rk3528_combphy_grfcfgs,
573 .combphy_cfg = rk3528_combphy_cfg,
574 };
575
rk3562_combphy_cfg(struct rockchip_combphy_priv * priv)576 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
577 {
578 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
579 struct clk *refclk = NULL;
580 unsigned long rate;
581 int i;
582 u32 val;
583
584 /* Configure PHY reference clock frequency */
585 for (i = 0; i < priv->num_clks; i++) {
586 if (!strncmp(priv->clks[i].id, "refclk", 6)) {
587 refclk = priv->clks[i].clk;
588 break;
589 }
590 }
591
592 if (!refclk) {
593 dev_err(priv->dev, "No refclk found\n");
594 return -EINVAL;
595 }
596
597 switch (priv->mode) {
598 case PHY_TYPE_PCIE:
599 /* Set SSC downward spread spectrum */
600 val = readl(priv->mmio + (0x1f << 2));
601 val &= ~GENMASK(5, 4);
602 val |= 0x01 << 4;
603 writel(val, priv->mmio + 0x7c);
604
605 param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
606 param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
607 param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
608 param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
609 break;
610 case PHY_TYPE_USB3:
611 /* Set SSC downward spread spectrum */
612 val = readl(priv->mmio + (0x1f << 2));
613 val &= ~GENMASK(5, 4);
614 val |= 0x01 << 4;
615 writel(val, priv->mmio + 0x7c);
616
617 /* Enable adaptive CTLE for USB3.0 Rx */
618 val = readl(priv->mmio + (0x0e << 2));
619 val &= ~GENMASK(0, 0);
620 val |= 0x01;
621 writel(val, priv->mmio + (0x0e << 2));
622
623 /* Set PLL KVCO fine tuning signals */
624 val = readl(priv->mmio + (0x20 << 2));
625 val &= ~(0x7 << 2);
626 val |= 0x2 << 2;
627 writel(val, priv->mmio + (0x20 << 2));
628
629 /* Set PLL LPF R1 to su_trim[10:7]=1001 */
630 writel(0x4, priv->mmio + (0xb << 2));
631
632 /* Set PLL input clock divider 1/2 */
633 val = readl(priv->mmio + (0x5 << 2));
634 val &= ~(0x3 << 6);
635 val |= 0x1 << 6;
636 writel(val, priv->mmio + (0x5 << 2));
637
638 /* Set PLL loop divider */
639 writel(0x32, priv->mmio + (0x11 << 2));
640
641 /* Set PLL KVCO to min and set PLL charge pump current to max */
642 writel(0xf0, priv->mmio + (0xa << 2));
643
644 /* Set Rx squelch input filler bandwidth */
645 writel(0x0e, priv->mmio + (0x14 << 2));
646
647 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
648 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
649 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
650 param_write(priv->phy_grf, &cfg->usb_mode_set, true);
651 break;
652 default:
653 dev_err(priv->dev, "incompatible PHY type\n");
654 return -EINVAL;
655 }
656
657 rate = clk_get_rate(refclk);
658
659 switch (rate) {
660 case 24000000:
661 if (priv->mode == PHY_TYPE_USB3) {
662 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
663 val = readl(priv->mmio + (0x0e << 2));
664 val &= ~GENMASK(7, 6);
665 val |= 0x01 << 6;
666 writel(val, priv->mmio + (0x0e << 2));
667
668 val = readl(priv->mmio + (0x0f << 2));
669 val &= ~GENMASK(7, 0);
670 val |= 0x5f;
671 writel(val, priv->mmio + (0x0f << 2));
672 }
673 break;
674 case 25000000:
675 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
676 break;
677 case 100000000:
678 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
679 if (priv->mode == PHY_TYPE_PCIE) {
680 /* PLL KVCO tuning fine */
681 val = readl(priv->mmio + (0x20 << 2));
682 val &= ~(0x7 << 2);
683 val |= 0x2 << 2;
684 writel(val, priv->mmio + (0x20 << 2));
685
686 /* Enable controlling random jitter, aka RMJ */
687 writel(0x4, priv->mmio + (0xb << 2));
688
689 val = readl(priv->mmio + (0x5 << 2));
690 val &= ~(0x3 << 6);
691 val |= 0x1 << 6;
692 writel(val, priv->mmio + (0x5 << 2));
693
694 writel(0x32, priv->mmio + (0x11 << 2));
695 writel(0xf0, priv->mmio + (0xa << 2));
696
697 /* CKDRV output swing adjust to 650mv */
698 val = readl(priv->mmio + (0xd << 2));
699 val &= ~(0xf << 1);
700 val |= (0xb << 1);
701 writel(val, priv->mmio + (0xd << 2));
702 }
703 break;
704 default:
705 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
706 return -EINVAL;
707 }
708
709 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
710 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
711 if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
712 val = readl(priv->mmio + (0xc << 2));
713 val |= 0x3 << 4 | 0x1 << 7;
714 writel(val, priv->mmio + (0xc << 2));
715
716 val = readl(priv->mmio + (0xd << 2));
717 val |= 0x1;
718 writel(val, priv->mmio + (0xd << 2));
719 }
720 }
721
722 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
723 val = readl(priv->mmio + (0x7 << 2));
724 val |= BIT(4);
725 writel(val, priv->mmio + (0x7 << 2));
726 }
727
728 return 0;
729 }
730
731 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
732 /* pipe-phy-grf */
733 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
734 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
735 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
736 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
737 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
738 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
739 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
740 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
741 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
742 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
743 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
744 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
745 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
746 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
747 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
748 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
749 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
750 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
751 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
752 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 },
753 /* peri-grf */
754 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 },
755 };
756
757 static const struct clk_bulk_data rk3562_clks[] = {
758 { .id = "refclk" },
759 { .id = "apbclk" },
760 { .id = "pipe_clk" },
761 };
762
763 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
764 .num_clks = ARRAY_SIZE(rk3562_clks),
765 .clks = rk3562_clks,
766 .grfcfg = &rk3562_combphy_grfcfgs,
767 .combphy_cfg = rk3562_combphy_cfg,
768 .force_det_out = true,
769 };
770
rk3568_combphy_cfg(struct rockchip_combphy_priv * priv)771 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
772 {
773 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
774 struct clk *refclk = NULL;
775 unsigned long rate;
776 int i;
777 u32 val;
778
779 /* Configure PHY reference clock frequency */
780 for (i = 0; i < priv->num_clks; i++) {
781 if (!strncmp(priv->clks[i].id, "refclk", 6)) {
782 refclk = priv->clks[i].clk;
783 break;
784 }
785 }
786
787 if (!refclk) {
788 dev_err(priv->dev, "No refclk found\n");
789 return -EINVAL;
790 }
791
792 switch (priv->mode) {
793 case PHY_TYPE_PCIE:
794 /* Set SSC downward spread spectrum */
795 val = readl(priv->mmio + (0x1f << 2));
796 val &= ~GENMASK(5, 4);
797 val |= 0x01 << 4;
798 writel(val, priv->mmio + 0x7c);
799
800 param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
801 param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
802 param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
803 param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
804 break;
805 case PHY_TYPE_USB3:
806 /* Set SSC downward spread spectrum */
807 val = readl(priv->mmio + (0x1f << 2));
808 val &= ~GENMASK(5, 4);
809 val |= 0x01 << 4;
810 writel(val, priv->mmio + 0x7c);
811
812 /* Enable adaptive CTLE for USB3.0 Rx */
813 val = readl(priv->mmio + (0x0e << 2));
814 val &= ~GENMASK(0, 0);
815 val |= 0x01;
816 writel(val, priv->mmio + (0x0e << 2));
817
818 /* Set PLL KVCO fine tuning signals */
819 val = readl(priv->mmio + (0x20 << 2));
820 val &= ~(0x7 << 2);
821 val |= 0x2 << 2;
822 writel(val, priv->mmio + (0x20 << 2));
823
824 /* Set PLL LPF R1 to su_trim[10:7]=1001 */
825 writel(0x4, priv->mmio + (0xb << 2));
826
827 /* Set PLL input clock divider 1/2 */
828 val = readl(priv->mmio + (0x5 << 2));
829 val &= ~(0x3 << 6);
830 val |= 0x1 << 6;
831 writel(val, priv->mmio + (0x5 << 2));
832
833 /* Set PLL loop divider */
834 writel(0x32, priv->mmio + (0x11 << 2));
835
836 /* Set PLL KVCO to min and set PLL charge pump current to max */
837 writel(0xf0, priv->mmio + (0xa << 2));
838
839 /* Set Rx squelch input filler bandwidth */
840 writel(0x0e, priv->mmio + (0x14 << 2));
841
842 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
843 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
844 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
845 param_write(priv->phy_grf, &cfg->usb_mode_set, true);
846 break;
847 case PHY_TYPE_SATA:
848 writel(0x41, priv->mmio + 0x38);
849 writel(0x8F, priv->mmio + 0x18);
850 param_write(priv->phy_grf, &cfg->con0_for_sata, true);
851 param_write(priv->phy_grf, &cfg->con1_for_sata, true);
852 param_write(priv->phy_grf, &cfg->con2_for_sata, true);
853 param_write(priv->phy_grf, &cfg->con3_for_sata, true);
854 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
855 break;
856 case PHY_TYPE_SGMII:
857 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
858 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
859 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
860 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
861 break;
862 case PHY_TYPE_QSGMII:
863 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
864 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
865 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
866 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
867 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
868 break;
869 default:
870 dev_err(priv->dev, "incompatible PHY type\n");
871 return -EINVAL;
872 }
873
874 rate = clk_get_rate(refclk);
875
876 switch (rate) {
877 case 24000000:
878 if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
879 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
880 val = readl(priv->mmio + (0x0e << 2));
881 val &= ~GENMASK(7, 6);
882 val |= 0x01 << 6;
883 writel(val, priv->mmio + (0x0e << 2));
884
885 val = readl(priv->mmio + (0x0f << 2));
886 val &= ~GENMASK(7, 0);
887 val |= 0x5f;
888 writel(val, priv->mmio + (0x0f << 2));
889 }
890 break;
891 case 25000000:
892 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
893 break;
894 case 100000000:
895 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
896 if (priv->mode == PHY_TYPE_PCIE) {
897 /* PLL KVCO tuning fine */
898 val = readl(priv->mmio + (0x20 << 2));
899 val &= ~(0x7 << 2);
900 val |= 0x2 << 2;
901 writel(val, priv->mmio + (0x20 << 2));
902
903 /* Enable controlling random jitter, aka RMJ */
904 writel(0x4, priv->mmio + (0xb << 2));
905
906 val = readl(priv->mmio + (0x5 << 2));
907 val &= ~(0x3 << 6);
908 val |= 0x1 << 6;
909 writel(val, priv->mmio + (0x5 << 2));
910
911 writel(0x32, priv->mmio + (0x11 << 2));
912 writel(0xf0, priv->mmio + (0xa << 2));
913 } else if (priv->mode == PHY_TYPE_SATA) {
914 /* downward spread spectrum +500ppm */
915 val = readl(priv->mmio + (0x1f << 2));
916 val &= ~GENMASK(7, 4);
917 val |= 0x50;
918 writel(val, priv->mmio + (0x1f << 2));
919 }
920 break;
921 default:
922 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
923 return -EINVAL;
924 }
925
926 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
927 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
928 if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
929 val = readl(priv->mmio + (0xc << 2));
930 val |= 0x3 << 4 | 0x1 << 7;
931 writel(val, priv->mmio + (0xc << 2));
932
933 val = readl(priv->mmio + (0xd << 2));
934 val |= 0x1;
935 writel(val, priv->mmio + (0xd << 2));
936 }
937 }
938
939 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
940 val = readl(priv->mmio + (0x7 << 2));
941 val |= BIT(4);
942 writel(val, priv->mmio + (0x7 << 2));
943 }
944
945 return 0;
946 }
947
948 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
949 /* pipe-phy-grf */
950 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
951 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
952 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
953 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
954 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
955 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
956 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
957 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
958 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
959 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
960 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
961 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
962 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
963 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
964 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
965 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
966 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
967 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
968 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
969 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
970 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
971 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
972 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
973 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
974 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
975 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
976 /* pipe-grf */
977 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
978 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 },
979 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
980 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 },
981 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 },
982 };
983
984 static const struct clk_bulk_data rk3568_clks[] = {
985 { .id = "refclk" },
986 { .id = "apbclk" },
987 { .id = "pipe_clk" },
988 };
989
990 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
991 .num_clks = ARRAY_SIZE(rk3568_clks),
992 .clks = rk3568_clks,
993 .grfcfg = &rk3568_combphy_grfcfgs,
994 .combphy_cfg = rk3568_combphy_cfg,
995 .force_det_out = true,
996 };
997
rk3588_combphy_cfg(struct rockchip_combphy_priv * priv)998 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
999 {
1000 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
1001 struct clk *refclk = NULL;
1002 unsigned long rate;
1003 int i;
1004 u32 val;
1005
1006 /* Configure PHY reference clock frequency */
1007 for (i = 0; i < priv->num_clks; i++) {
1008 if (!strncmp(priv->clks[i].id, "refclk", 6)) {
1009 refclk = priv->clks[i].clk;
1010 break;
1011 }
1012 }
1013
1014 if (!refclk) {
1015 dev_err(priv->dev, "No refclk found\n");
1016 return -EINVAL;
1017 }
1018
1019 switch (priv->mode) {
1020 case PHY_TYPE_PCIE:
1021 /* Set SSC downward spread spectrum */
1022 val = readl(priv->mmio + (0x1f << 2));
1023 val &= ~GENMASK(5, 4);
1024 val |= 0x01 << 4;
1025 writel(val, priv->mmio + 0x7c);
1026
1027 param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
1028 param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
1029 param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
1030 param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
1031 break;
1032 case PHY_TYPE_USB3:
1033 /* Set SSC downward spread spectrum */
1034 val = readl(priv->mmio + (0x1f << 2));
1035 val &= ~GENMASK(5, 4);
1036 val |= 0x01 << 4;
1037 writel(val, priv->mmio + 0x7c);
1038
1039 /* Enable adaptive CTLE for USB3.0 Rx */
1040 val = readl(priv->mmio + (0x0e << 2));
1041 val &= ~GENMASK(0, 0);
1042 val |= 0x01;
1043 writel(val, priv->mmio + (0x0e << 2));
1044
1045 /* Set PLL KVCO fine tuning signals */
1046 val = readl(priv->mmio + (0x20 << 2));
1047 val &= ~(0x7 << 2);
1048 val |= 0x2 << 2;
1049 writel(val, priv->mmio + (0x20 << 2));
1050
1051 /* Set PLL LPF R1 to su_trim[10:7]=1001 */
1052 writel(0x4, priv->mmio + (0xb << 2));
1053
1054 /* Set PLL input clock divider 1/2 */
1055 val = readl(priv->mmio + (0x5 << 2));
1056 val &= ~(0x3 << 6);
1057 val |= 0x1 << 6;
1058 writel(val, priv->mmio + (0x5 << 2));
1059
1060 /* Set PLL loop divider */
1061 writel(0x32, priv->mmio + (0x11 << 2));
1062
1063 /* Set PLL KVCO to min and set PLL charge pump current to max */
1064 writel(0xf0, priv->mmio + (0xa << 2));
1065
1066 /* Set Rx squelch input filler bandwidth */
1067 writel(0x0d, priv->mmio + (0x14 << 2));
1068
1069 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
1070 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
1071 param_write(priv->phy_grf, &cfg->usb_mode_set, true);
1072 break;
1073 case PHY_TYPE_SATA:
1074 /* Enable adaptive CTLE for SATA Rx */
1075 val = readl(priv->mmio + (0x0e << 2));
1076 val &= ~GENMASK(0, 0);
1077 val |= 0x01;
1078 writel(val, priv->mmio + (0x0e << 2));
1079 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
1080 writel(0x8F, priv->mmio + (0x06 << 2));
1081
1082 param_write(priv->phy_grf, &cfg->con0_for_sata, true);
1083 param_write(priv->phy_grf, &cfg->con1_for_sata, true);
1084 param_write(priv->phy_grf, &cfg->con2_for_sata, true);
1085 param_write(priv->phy_grf, &cfg->con3_for_sata, true);
1086 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
1087 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
1088 break;
1089 case PHY_TYPE_SGMII:
1090 case PHY_TYPE_QSGMII:
1091 default:
1092 dev_err(priv->dev, "incompatible PHY type\n");
1093 return -EINVAL;
1094 }
1095
1096 rate = clk_get_rate(refclk);
1097
1098 switch (rate) {
1099 case 24000000:
1100 param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
1101 if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
1102 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
1103 val = readl(priv->mmio + (0x0e << 2));
1104 val &= ~GENMASK(7, 6);
1105 val |= 0x01 << 6;
1106 writel(val, priv->mmio + (0x0e << 2));
1107
1108 val = readl(priv->mmio + (0x0f << 2));
1109 val &= ~GENMASK(7, 0);
1110 val |= 0x5f;
1111 writel(val, priv->mmio + (0x0f << 2));
1112 } else if (priv->mode == PHY_TYPE_PCIE) {
1113 /* PLL KVCO tuning fine */
1114 val = readl(priv->mmio + (0x20 << 2));
1115 val &= ~GENMASK(4, 2);
1116 val |= 0x4 << 2;
1117 writel(val, priv->mmio + (0x20 << 2));
1118
1119 /* Set up rx_trim */
1120 val = 0x0;
1121 writel(val, priv->mmio + (0x1b << 2));
1122
1123 /* Set up su_trim: T0_1 */
1124 val = 0x90;
1125 writel(val, priv->mmio + (0xa << 2));
1126 val = 0x02;
1127 writel(val, priv->mmio + (0xb << 2));
1128 val = 0x57;
1129 writel(val, priv->mmio + (0xd << 2));
1130
1131 val = 0x5f;
1132 writel(val, priv->mmio + (0xf << 2));
1133 }
1134 break;
1135 case 25000000:
1136 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
1137 break;
1138 case 100000000:
1139 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
1140 if (priv->mode == PHY_TYPE_PCIE) {
1141 /* gate_tx_pck_sel length select work for L1SS */
1142 val = 0xc0;
1143 writel(val, priv->mmio + 0x74);
1144
1145 /* PLL KVCO tuning fine */
1146 val = readl(priv->mmio + (0x20 << 2));
1147 val &= ~GENMASK(4, 2);
1148 val |= 0x4 << 2;
1149 writel(val, priv->mmio + (0x20 << 2));
1150
1151 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
1152 val = 0x4c;
1153 writel(val, priv->mmio + (0x1b << 2));
1154
1155 /* Set up su_trim: T3_P1 650mv */
1156 val = 0x90;
1157 writel(val, priv->mmio + (0xa << 2));
1158 val = 0x43;
1159 writel(val, priv->mmio + (0xb << 2));
1160 val = 0x88;
1161 writel(val, priv->mmio + (0xc << 2));
1162 val = 0x56;
1163 writel(val, priv->mmio + (0xd << 2));
1164 } else if (priv->mode == PHY_TYPE_SATA) {
1165 /* downward spread spectrum +500ppm */
1166 val = readl(priv->mmio + (0x1f << 2));
1167 val &= ~GENMASK(7, 4);
1168 val |= 0x50;
1169 writel(val, priv->mmio + (0x1f << 2));
1170
1171 /* ssc ppm adjust to 3500ppm */
1172 val = readl(priv->mmio + (0x9 << 2));
1173 val &= ~GENMASK(3, 0);
1174 val |= 0x7;
1175 writel(val, priv->mmio + (0x9 << 2));
1176 }
1177 break;
1178 default:
1179 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
1180 return -EINVAL;
1181 }
1182
1183 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
1184 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
1185 if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
1186 val = 0x10;
1187 writel(val, priv->mmio + (0x20 << 2));
1188
1189 val = 0x0c;
1190 writel(val, priv->mmio + (0x1b << 2));
1191
1192 /* Set up su_trim: T3_P1 650mv */
1193 val = 0x90;
1194 writel(val, priv->mmio + (0xa << 2));
1195 val = 0x43;
1196 writel(val, priv->mmio + (0xb << 2));
1197 val = 0x88;
1198 writel(val, priv->mmio + (0xc << 2));
1199 val = 0x56;
1200 writel(val, priv->mmio + (0xd << 2));
1201 }
1202 }
1203
1204 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
1205 val = readl(priv->mmio + (0x7 << 2));
1206 val |= BIT(4);
1207 writel(val, priv->mmio + (0x7 << 2));
1208
1209 if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) {
1210 /* Xin24M T0_1 650mV */
1211 writel(0x00, priv->mmio + (0x10 << 2));
1212 writel(0x32, priv->mmio + (0x11 << 2));
1213 writel(0x00, priv->mmio + (0x1b << 2));
1214 writel(0x90, priv->mmio + (0x0a << 2));
1215 writel(0x02, priv->mmio + (0x0b << 2));
1216 writel(0x08, priv->mmio + (0x0c << 2));
1217 writel(0x57, priv->mmio + (0x0d << 2));
1218 writel(0x40, priv->mmio + (0x0e << 2));
1219 writel(0x5f, priv->mmio + (0x0f << 2));
1220 writel(0x10, priv->mmio + (0x20 << 2));
1221 }
1222 }
1223
1224 return 0;
1225 }
1226
1227 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
1228 /* pipe-phy-grf */
1229 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
1230 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
1231 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
1232 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
1233 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
1234 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
1235 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
1236 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
1237 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
1238 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
1239 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
1240 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
1241 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
1242 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
1243 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
1244 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
1245 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
1246 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
1247 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
1248 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
1249 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
1250 /* pipe-grf */
1251 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
1252 .pipe_con1_for_sata = { 0x0004, 2, 0, 0x00, 0x2 },
1253 };
1254
1255 static const struct clk_bulk_data rk3588_clks[] = {
1256 { .id = "refclk" },
1257 { .id = "apbclk" },
1258 { .id = "phpclk" },
1259 };
1260
1261 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
1262 .num_clks = ARRAY_SIZE(rk3588_clks),
1263 .clks = rk3588_clks,
1264 .grfcfg = &rk3588_combphy_grfcfgs,
1265 .combphy_cfg = rk3588_combphy_cfg,
1266 .force_det_out = true,
1267 };
1268
1269 static const struct of_device_id rockchip_combphy_of_match[] = {
1270 {
1271 .compatible = "rockchip,rk3528-naneng-combphy",
1272 .data = &rk3528_combphy_cfgs,
1273 },
1274 {
1275 .compatible = "rockchip,rk3562-naneng-combphy",
1276 .data = &rk3562_combphy_cfgs,
1277 },
1278 {
1279 .compatible = "rockchip,rk3568-naneng-combphy",
1280 .data = &rk3568_combphy_cfgs,
1281 },
1282 {
1283 .compatible = "rockchip,rk3588-naneng-combphy",
1284 .data = &rk3588_combphy_cfgs,
1285 },
1286 { },
1287 };
1288 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
1289
1290 static struct platform_driver rockchip_combphy_driver = {
1291 .probe = rockchip_combphy_probe,
1292 .driver = {
1293 .name = "naneng-combphy",
1294 .of_match_table = rockchip_combphy_of_match,
1295 },
1296 };
1297 module_platform_driver(rockchip_combphy_driver);
1298
1299 MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
1300 MODULE_LICENSE("GPL v2");
1301