1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * at91-pcm.h - ALSA PCM interface for the Atmel AT91 SoC. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2005 SAN People 6*4882a593Smuzhiyun * Copyright (C) 2008 Atmel 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Authors: Sedji Gaouaou <sedji.gaouaou@atmel.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Based on at91-pcm. by: 11*4882a593Smuzhiyun * Frank Mandarino <fmandarino@endrelia.com> 12*4882a593Smuzhiyun * Copyright 2006 Endrelia Technologies Inc. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Based on pxa2xx-pcm.c by: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * Author: Nicolas Pitre 17*4882a593Smuzhiyun * Created: Nov 30, 2004 18*4882a593Smuzhiyun * Copyright: (C) 2004 MontaVista Software, Inc. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef _ATMEL_PCM_H 22*4882a593Smuzhiyun #define _ATMEL_PCM_H 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <linux/atmel-ssc.h> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define ATMEL_SSC_DMABUF_SIZE (64 * 1024) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * Registers and status bits that are required by the PCM driver. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun struct atmel_pdc_regs { 32*4882a593Smuzhiyun unsigned int xpr; /* PDC recv/trans pointer */ 33*4882a593Smuzhiyun unsigned int xcr; /* PDC recv/trans counter */ 34*4882a593Smuzhiyun unsigned int xnpr; /* PDC next recv/trans pointer */ 35*4882a593Smuzhiyun unsigned int xncr; /* PDC next recv/trans counter */ 36*4882a593Smuzhiyun unsigned int ptcr; /* PDC transfer control */ 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct atmel_ssc_mask { 40*4882a593Smuzhiyun u32 ssc_enable; /* SSC recv/trans enable */ 41*4882a593Smuzhiyun u32 ssc_disable; /* SSC recv/trans disable */ 42*4882a593Smuzhiyun u32 ssc_error; /* SSC error conditions */ 43*4882a593Smuzhiyun u32 ssc_endx; /* SSC ENDTX or ENDRX */ 44*4882a593Smuzhiyun u32 ssc_endbuf; /* SSC TXBUFE or RXBUFF */ 45*4882a593Smuzhiyun u32 pdc_enable; /* PDC recv/trans enable */ 46*4882a593Smuzhiyun u32 pdc_disable; /* PDC recv/trans disable */ 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * This structure, shared between the PCM driver and the interface, 51*4882a593Smuzhiyun * contains all information required by the PCM driver to perform the 52*4882a593Smuzhiyun * PDC DMA operation. All fields except dma_intr_handler() are initialized 53*4882a593Smuzhiyun * by the interface. The dma_intr_handler() pointer is set by the PCM 54*4882a593Smuzhiyun * driver and called by the interface SSC interrupt handler if it is 55*4882a593Smuzhiyun * non-NULL. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun struct atmel_pcm_dma_params { 58*4882a593Smuzhiyun char *name; /* stream identifier */ 59*4882a593Smuzhiyun int pdc_xfer_size; /* PDC counter increment in bytes */ 60*4882a593Smuzhiyun struct ssc_device *ssc; /* SSC device for stream */ 61*4882a593Smuzhiyun struct atmel_pdc_regs *pdc; /* PDC receive or transmit registers */ 62*4882a593Smuzhiyun struct atmel_ssc_mask *mask; /* SSC & PDC status bits */ 63*4882a593Smuzhiyun struct snd_pcm_substream *substream; 64*4882a593Smuzhiyun void (*dma_intr_handler)(u32, struct snd_pcm_substream *); 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * SSC register access (since ssc_writel() / ssc_readl() require literal name) 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define ssc_readx(base, reg) (__raw_readl((base) + (reg))) 71*4882a593Smuzhiyun #define ssc_writex(base, reg, value) __raw_writel((value), (base) + (reg)) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_ATMEL_SOC_PDC) 74*4882a593Smuzhiyun int atmel_pcm_pdc_platform_register(struct device *dev); 75*4882a593Smuzhiyun #else atmel_pcm_pdc_platform_register(struct device * dev)76*4882a593Smuzhiyunstatic inline int atmel_pcm_pdc_platform_register(struct device *dev) 77*4882a593Smuzhiyun { 78*4882a593Smuzhiyun return 0; 79*4882a593Smuzhiyun } 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_ATMEL_SOC_DMA) 83*4882a593Smuzhiyun int atmel_pcm_dma_platform_register(struct device *dev); 84*4882a593Smuzhiyun #else atmel_pcm_dma_platform_register(struct device * dev)85*4882a593Smuzhiyunstatic inline int atmel_pcm_dma_platform_register(struct device *dev) 86*4882a593Smuzhiyun { 87*4882a593Smuzhiyun return 0; 88*4882a593Smuzhiyun } 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* _ATMEL_PCM_H */ 92