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/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Drockchip_dmc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-structs.h>
14 #include <linux/arm-smccc.h>
171 "ddr3a1_ddr4a9_de-skew",
172 "ddr3a0_ddr4a10_de-skew",
173 "ddr3a3_ddr4a6_de-skew",
174 "ddr3a2_ddr4a4_de-skew",
175 "ddr3a5_ddr4a8_de-skew",
176 "ddr3a4_ddr4a5_de-skew",
177 "ddr3a7_ddr4a11_de-skew",
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Dpx30-ddr4p416dd6-timing.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /* CA de-skew, one step is 47.8ps, range 0-15 */
6 ddr3a1_ddr4a9_de-skew = <0>;
7 ddr3a0_ddr4a10_de-skew = <5>;
8 ddr3a3_ddr4a6_de-skew = <2>;
9 ddr3a2_ddr4a4_de-skew = <4>;
10 ddr3a5_ddr4a8_de-skew = <2>;
11 ddr3a4_ddr4a5_de-skew = <1>;
12 ddr3a7_ddr4a11_de-skew = <2>;
13 ddr3a6_ddr4a7_de-skew = <0>;
[all …]
H A Drk3328-box-plus-dram-timing.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip-ddr.h>
7 #include <dt-bindings/memory/rk3328-dram.h>
10 /* CA de-skew, one step is 47.8ps, range 0-15 */
11 ddr3a1_ddr4a9_de-skew = <0>;
12 ddr3a0_ddr4a10_de-skew = <0>;
13 ddr3a3_ddr4a6_de-skew = <1>;
14 ddr3a2_ddr4a4_de-skew = <1>;
15 ddr3a5_ddr4a8_de-skew = <0>;
16 ddr3a4_ddr4a5_de-skew = <2>;
[all …]
H A Drk3328-dram-2layer-timing.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rockchip-ddr.h>
8 #include <dt-bindings/memory/rk3328-dram.h>
11 /* CA de-skew, one step is 47.8ps, range 0-15 */
12 ddr3a1_ddr4a9_de-skew = <2>;
13 ddr3a0_ddr4a10_de-skew = <4>;
14 ddr3a3_ddr4a6_de-skew = <6>;
15 ddr3a2_ddr4a4_de-skew = <5>;
16 ddr3a5_ddr4a8_de-skew = <7>;
17 ddr3a4_ddr4a5_de-skew = <7>;
[all …]
H A Drk3328-dram-default-timing.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rockchip-ddr.h>
8 #include <dt-bindings/memory/rk3328-dram.h>
12 compatible = "rockchip,ddr-timing";
64 /* CA de-skew, one step is 47.8ps, range 0-15 */
65 ddr3a1_ddr4a9_de-skew = <7>;
66 ddr3a0_ddr4a10_de-skew = <7>;
67 ddr3a3_ddr4a6_de-skew = <8>;
68 ddr3a2_ddr4a4_de-skew = <8>;
69 ddr3a5_ddr4a8_de-skew = <7>;
[all …]
H A Drk1808-dram-default-timing.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip-ddr.h>
7 #include <dt-bindings/memory/rk1808-dram.h>
11 compatible = "rockchip,ddr-timing";
82 * CA de-skew, one step is 15ps, range 0-31
85 a0_ddr3a9_de-skew = <7>;
86 a1_ddr3a14_de-skew = <7>;
87 a2_ddr3a13_de-skew = <7>;
88 a3_ddr3a11_de-skew = <7>;
89 a4_ddr3a2_de-skew = <7>;
[all …]
H A Dpx30-dram-default-timing.dtsi4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rockchip-ddr.h>
8 #include <dt-bindings/memory/px30-dram.h>
12 compatible = "rockchip,ddr-timing";
82 /* CA de-skew, one step is 47.8ps, range 0-15 */
83 ddr3a1_ddr4a9_de-skew = <6>;
84 ddr3a0_ddr4a10_de-skew = <7>;
85 ddr3a3_ddr4a6_de-skew = <7>;
86 ddr3a2_ddr4a4_de-skew = <7>;
87 ddr3a5_ddr4a8_de-skew = <7>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1126-dram-default-timing.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip-ddr.h>
7 #include <dt-bindings/memory/rv1126-dram.h>
11 compatible = "rockchip,ddr-timing";
82 * CA de-skew, one step is 20ps, range 0-63
83 * name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew
85 a0_a3_a3_cke1-a_de-skew = <7>;
86 a1_ba1_null_cke0-b_de-skew = <7>;
87 a2_a9_a9_a4-a_de-skew = <7>;
88 a3_a15_null_a5-b_de-skew = <7>;
[all …]
H A Dsocfpga_cyclone5_socrates.dts2 * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
33 u-boot,dm-pre-reloc;
39 phy-mode = "rgmii";
41 rxd0-skew-ps = <0>;
42 rxd1-skew-ps = <0>;
43 rxd2-skew-ps = <0>;
44 rxd3-skew-ps = <0>;
45 txen-skew-ps = <0>;
[all …]
H A Dsocfpga_cyclone5_sockit.dts2 * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
29 u-boot,dm-pre-reloc;
35 phy-mode = "rgmii";
37 rxd0-skew-ps = <0>;
38 rxd1-skew-ps = <0>;
39 rxd2-skew-ps = <0>;
40 rxd3-skew-ps = <0>;
41 txen-skew-ps = <0>;
[all …]
H A Dsocfpga_cyclone5_vining_fpga.dts2 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
29 u-boot,dm-pre-reloc;
35 phy-mode = "rgmii";
37 rxd0-skew-ps = <0>;
38 rxd1-skew-ps = <0>;
39 rxd2-skew-ps = <0>;
40 rxd3-skew-ps = <0>;
41 txen-skew-ps = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drv1126-dram-default-timing.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip-ddr.h>
7 #include <dt-bindings/memory/rv1126-dram.h>
11 compatible = "rockchip,ddr-timing";
82 * CA de-skew, one step is 20ps, range 0-63
83 * name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew
85 a0_a3_a3_cke1-a_de-skew = <7>;
86 a1_ba1_null_cke0-b_de-skew = <7>;
87 a2_a9_a9_a4-a_de-skew = <7>;
88 a3_a15_null_a5-b_de-skew = <7>;
[all …]
H A Dsocfpga_cyclone5_de0_nano_soc.dts1 // SPDX-License-Identifier: GPL-2.0
9 model = "Terasic DE-0(Atlas)";
10 compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
27 regulator_3_3v: 3-3-v-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
35 compatible = "gpio-leds";
[all …]
H A Dsocfpga_cyclone5_sockit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
10 compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
36 linux,default-trigger = "heartbeat";
42 linux,default-trigger = "heartbeat";
48 linux,default-trigger = "heartbeat";
54 linux,default-trigger = "heartbeat";
58 gpio-keys {
[all …]
H A Dsocfpga_cyclone5_vining_fpga.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
3 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
68 regulator-usb-nrst {
69 compatible = "regulator-fixed";
[all …]
H A Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
5 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-cec-fixed {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
29 stdout-path = "serial0:115200n8";
32 hdmi-out {
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/sm750fb/
H A Dddk750_sii164.c1 // SPDX-License-Identifier: GPL-2.0
79 * edge_select - Edge Select:
84 * bus_select - Input Bus Select:
85 * 0 = Input data bus is 12-bits wide
86 * 1 = Input data bus is 24-bits wide
87 * dual_edge_clk_select - Dual Edge Clock Select
90 * hsync_enable - Horizontal Sync Enable:
93 * vsync_enable - Vertical Sync Enable:
96 * deskew_enable - De-skewing Enable:
97 * 0 = De-skew disabled
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/
H A Dti,tfp410.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomi Valkeinen <tomi.valkeinen@ti.com>
11 - Jyri Sarha <jsarha@ti.com>
21 powerdown-gpios:
26 Data de-skew value in 350ps increments, from 0 to 7, as configured
27 through the DK[3:1] pins. The de-skew multiplier is computed as
28 (DK[3:1] - 4), so it ranges from -4 to 3.
37 Documentation/devicetree/bindings/media/video-interfaces.txt
[all …]
/OK3568_Linux_fs/u-boot/board/spear/x600/
H A Dx600.c5 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
7 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/mach-types.h>
31 * power-up. Otherwise the RTC is halted. in board_init()
46 2 * CONFIG_ENV_SECT_SIZE - 1, in board_late_init()
56 * board_nand_init - Board specific NAND initialization
68 if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) in board_nand_init()
82 printf("PHY KSZ9031 detected - "); in board_phy_config()
86 /* control data pad skew - devaddr = 0x02, register = 0x04 */ in board_phy_config()
91 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ in board_phy_config()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage-memphis.cfg3 # Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 # SPDX-License-Identifier: GPL-2.0+
10 # Refer doc/README.kwbimage for more details about how-to configure
18 # bit 3-0: MPPSel0 2, NF_IO[2]
19 # bit 7-4: MPPSel1 2, NF_IO[3]
20 # bit 12-8: MPPSel2 2, NF_IO[4]
21 # bit 15-12: MPPSel3 2, NF_IO[5]
22 # bit 19-16: MPPSel4 1, NF_IO[6]
23 # bit 23-20: MPPSel5 1, NF_IO[7]
24 # bit 27-24: MPPSel6 1, SYSRST_O
[all …]
/OK3568_Linux_fs/kernel/sound/core/seq/
H A Dseq_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 1998-1999 by Frank van de Pol <fvdpol@coil.demon.nl>
23 if (tmr->tempo < 1000000) in snd_seq_timer_set_tick_resolution()
24 tmr->tick.resolution = (tmr->tempo * 1000) / tmr->ppq; in snd_seq_timer_set_tick_resolution()
28 s = tmr->tempo % tmr->ppq; in snd_seq_timer_set_tick_resolution()
29 s = (s * 1000) / tmr->ppq; in snd_seq_timer_set_tick_resolution()
30 tmr->tick.resolution = (tmr->tempo / tmr->ppq) * 1000; in snd_seq_timer_set_tick_resolution()
31 tmr->tick.resolution += s; in snd_seq_timer_set_tick_resolution()
33 if (tmr->tick.resolution <= 0) in snd_seq_timer_set_tick_resolution()
34 tmr->tick.resolution = 1; in snd_seq_timer_set_tick_resolution()
[all …]
/OK3568_Linux_fs/u-boot/board/liebherr/mccmon6/
H A Dmccmon6.c2 * Copyright (C) 2016-2017
3 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <asm/mach-imx/spi.h>
18 #include <asm/mach-imx/boot_mode.h>
62 gd->ram_size = imx_ddr_size(); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
24 # Configure RGMII-0 interface pad voltage to 1.8V
29 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
30 # bit23-14: 0 required
33 # bit29-26: 0 required
34 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
[all …]
/OK3568_Linux_fs/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg5 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
17 # Configure RGMII-0/1 interface pad voltage to 1.8V
30 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
31 # bit23-14: 0 required
34 # bit29-26: 0 required
35 # bit31-30: 0b01 required
39 # bit3-0: 0 required
43 # bit11-7: 0 required
47 # bit17-15: 0 required
[all …]

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