1/* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/rockchip-ddr.h> 8#include <dt-bindings/memory/px30-dram.h> 9 10/ { 11 ddr_timing: ddr_timing { 12 compatible = "rockchip,ddr-timing"; 13 ddr2_speed_bin = <DDR2_DEFAULT>; 14 ddr3_speed_bin = <DDR3_DEFAULT>; 15 ddr4_speed_bin = <DDR4_DEFAULT>; 16 pd_idle = <13>; 17 sr_idle = <93>; 18 sr_mc_gate_idle = <0>; 19 srpd_lite_idle = <0>; 20 standby_idle = <0>; 21 22 auto_pd_dis_freq = <1066>; 23 auto_sr_dis_freq = <800>; 24 ddr2_dll_dis_freq = <300>; 25 ddr3_dll_dis_freq = <300>; 26 ddr4_dll_dis_freq = <625>; 27 phy_dll_dis_freq = <400>; 28 29 ddr2_odt_dis_freq = <100>; 30 phy_ddr2_odt_dis_freq = <100>; 31 ddr2_drv = <DDR2_DS_REDUCE>; 32 ddr2_odt = <DDR2_ODT_150ohm>; 33 phy_ddr2_ca_drv = <PHY_DDR3_RON_RTT_34ohm>; 34 phy_ddr2_ck_drv = <PHY_DDR3_RON_RTT_45ohm>; 35 phy_ddr2_dq_drv = <PHY_DDR3_RON_RTT_34ohm>; 36 phy_ddr2_odt = <PHY_DDR3_RON_RTT_225ohm>; 37 38 ddr3_odt_dis_freq = <400>; 39 phy_ddr3_odt_dis_freq = <400>; 40 ddr3_drv = <DDR3_DS_40ohm>; 41 ddr3_odt = <DDR3_ODT_120ohm>; 42 phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>; 43 phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>; 44 phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>; 45 phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>; 46 47 phy_lpddr2_odt_dis_freq = <666>; 48 lpddr2_drv = <LP2_DS_40ohm>; 49 phy_lpddr2_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>; 50 phy_lpddr2_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>; 51 phy_lpddr2_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>; 52 phy_lpddr2_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_DISABLE>; 53 54 lpddr3_odt_dis_freq = <400>; 55 phy_lpddr3_odt_dis_freq = <400>; 56 lpddr3_drv = <LP3_DS_40ohm>; 57 lpddr3_odt = <LP3_ODT_240ohm>; 58 phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>; 59 phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>; 60 phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>; 61 phy_lpddr3_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_240ohm>; 62 63 lpddr4_odt_dis_freq = <800>; 64 phy_lpddr4_odt_dis_freq = <800>; 65 lpddr4_drv = <LP4_PDDS_60ohm>; 66 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; 67 lpddr4_ca_odt = <LP4_CA_ODT_40ohm>; 68 phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_40ohm>; 69 phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_80ohm>; 70 phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_80ohm>; 71 phy_lpddr4_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_60ohm>; 72 73 ddr4_odt_dis_freq = <666>; 74 phy_ddr4_odt_dis_freq = <666>; 75 ddr4_drv = <DDR4_DS_34ohm>; 76 ddr4_odt = <DDR4_RTT_NOM_240ohm>; 77 phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>; 78 phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>; 79 phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>; 80 phy_ddr4_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_240ohm>; 81 82 /* CA de-skew, one step is 47.8ps, range 0-15 */ 83 ddr3a1_ddr4a9_de-skew = <6>; 84 ddr3a0_ddr4a10_de-skew = <7>; 85 ddr3a3_ddr4a6_de-skew = <7>; 86 ddr3a2_ddr4a4_de-skew = <7>; 87 ddr3a5_ddr4a8_de-skew = <7>; 88 ddr3a4_ddr4a5_de-skew = <7>; 89 ddr3a7_ddr4a11_de-skew = <7>; 90 ddr3a6_ddr4a7_de-skew = <6>; 91 ddr3a9_ddr4a0_de-skew = <7>; 92 ddr3a8_ddr4a13_de-skew = <7>; 93 ddr3a11_ddr4a3_de-skew = <7>; 94 ddr3a10_ddr4cs0_de-skew = <7>; 95 ddr3a13_ddr4a2_de-skew = <7>; 96 ddr3a12_ddr4ba1_de-skew = <7>; 97 ddr3a15_ddr4odt0_de-skew = <7>; 98 ddr3a14_ddr4a1_de-skew = <7>; 99 ddr3ba1_ddr4a15_de-skew = <7>; 100 ddr3ba0_ddr4bg0_de-skew = <7>; 101 ddr3ras_ddr4cke_de-skew = <7>; 102 ddr3ba2_ddr4ba0_de-skew = <7>; 103 ddr3we_ddr4bg1_de-skew = <7>; 104 ddr3cas_ddr4a12_de-skew = <7>; 105 ddr3ckn_ddr4ckn_de-skew = <7>; 106 ddr3ckp_ddr4ckp_de-skew = <7>; 107 ddr3cke_ddr4a16_de-skew = <7>; 108 ddr3odt0_ddr4a14_de-skew = <7>; 109 ddr3cs0_ddr4act_de-skew = <6>; 110 ddr3reset_ddr4reset_de-skew = <7>; 111 ddr3cs1_ddr4cs1_de-skew = <6>; 112 ddr3odt1_ddr4odt1_de-skew = <7>; 113 114 /* DATA de-skew 115 * RX one step is 25.1ps, range 0-15 116 * TX one step is 47.8ps, range 0-15 117 */ 118 cs0_dm0_rx_de-skew = <7>; 119 cs0_dm0_tx_de-skew = <7>; 120 cs0_dq0_rx_de-skew = <8>; 121 cs0_dq0_tx_de-skew = <8>; 122 cs0_dq1_rx_de-skew = <9>; 123 cs0_dq1_tx_de-skew = <8>; 124 cs0_dq2_rx_de-skew = <8>; 125 cs0_dq2_tx_de-skew = <8>; 126 cs0_dq3_rx_de-skew = <8>; 127 cs0_dq3_tx_de-skew = <8>; 128 cs0_dq4_rx_de-skew = <9>; 129 cs0_dq4_tx_de-skew = <8>; 130 cs0_dq5_rx_de-skew = <9>; 131 cs0_dq5_tx_de-skew = <8>; 132 cs0_dq6_rx_de-skew = <9>; 133 cs0_dq6_tx_de-skew = <8>; 134 cs0_dq7_rx_de-skew = <8>; 135 cs0_dq7_tx_de-skew = <8>; 136 cs0_dqs0_rx_de-skew = <6>; 137 cs0_dqs0p_tx_de-skew = <9>; 138 cs0_dqs0n_tx_de-skew = <9>; 139 140 cs0_dm1_rx_de-skew = <7>; 141 cs0_dm1_tx_de-skew = <6>; 142 cs0_dq8_rx_de-skew = <8>; 143 cs0_dq8_tx_de-skew = <7>; 144 cs0_dq9_rx_de-skew = <9>; 145 cs0_dq9_tx_de-skew = <7>; 146 cs0_dq10_rx_de-skew = <8>; 147 cs0_dq10_tx_de-skew = <8>; 148 cs0_dq11_rx_de-skew = <8>; 149 cs0_dq11_tx_de-skew = <7>; 150 cs0_dq12_rx_de-skew = <8>; 151 cs0_dq12_tx_de-skew = <8>; 152 cs0_dq13_rx_de-skew = <9>; 153 cs0_dq13_tx_de-skew = <7>; 154 cs0_dq14_rx_de-skew = <9>; 155 cs0_dq14_tx_de-skew = <8>; 156 cs0_dq15_rx_de-skew = <9>; 157 cs0_dq15_tx_de-skew = <7>; 158 cs0_dqs1_rx_de-skew = <7>; 159 cs0_dqs1p_tx_de-skew = <9>; 160 cs0_dqs1n_tx_de-skew = <9>; 161 162 cs0_dm2_rx_de-skew = <7>; 163 cs0_dm2_tx_de-skew = <7>; 164 cs0_dq16_rx_de-skew = <9>; 165 cs0_dq16_tx_de-skew = <9>; 166 cs0_dq17_rx_de-skew = <7>; 167 cs0_dq17_tx_de-skew = <9>; 168 cs0_dq18_rx_de-skew = <7>; 169 cs0_dq18_tx_de-skew = <8>; 170 cs0_dq19_rx_de-skew = <7>; 171 cs0_dq19_tx_de-skew = <9>; 172 cs0_dq20_rx_de-skew = <9>; 173 cs0_dq20_tx_de-skew = <9>; 174 cs0_dq21_rx_de-skew = <9>; 175 cs0_dq21_tx_de-skew = <9>; 176 cs0_dq22_rx_de-skew = <8>; 177 cs0_dq22_tx_de-skew = <9>; 178 cs0_dq23_rx_de-skew = <8>; 179 cs0_dq23_tx_de-skew = <9>; 180 cs0_dqs2_rx_de-skew = <6>; 181 cs0_dqs2p_tx_de-skew = <9>; 182 cs0_dqs2n_tx_de-skew = <9>; 183 184 cs0_dm3_rx_de-skew = <7>; 185 cs0_dm3_tx_de-skew = <7>; 186 cs0_dq24_rx_de-skew = <8>; 187 cs0_dq24_tx_de-skew = <8>; 188 cs0_dq25_rx_de-skew = <9>; 189 cs0_dq25_tx_de-skew = <9>; 190 cs0_dq26_rx_de-skew = <9>; 191 cs0_dq26_tx_de-skew = <8>; 192 cs0_dq27_rx_de-skew = <9>; 193 cs0_dq27_tx_de-skew = <8>; 194 cs0_dq28_rx_de-skew = <9>; 195 cs0_dq28_tx_de-skew = <9>; 196 cs0_dq29_rx_de-skew = <9>; 197 cs0_dq29_tx_de-skew = <9>; 198 cs0_dq30_rx_de-skew = <8>; 199 cs0_dq30_tx_de-skew = <8>; 200 cs0_dq31_rx_de-skew = <8>; 201 cs0_dq31_tx_de-skew = <8>; 202 cs0_dqs3_rx_de-skew = <7>; 203 cs0_dqs3p_tx_de-skew = <9>; 204 cs0_dqs3n_tx_de-skew = <9>; 205 206 cs1_dm0_rx_de-skew = <7>; 207 cs1_dm0_tx_de-skew = <7>; 208 cs1_dq0_rx_de-skew = <8>; 209 cs1_dq0_tx_de-skew = <8>; 210 cs1_dq1_rx_de-skew = <9>; 211 cs1_dq1_tx_de-skew = <8>; 212 cs1_dq2_rx_de-skew = <8>; 213 cs1_dq2_tx_de-skew = <8>; 214 cs1_dq3_rx_de-skew = <8>; 215 cs1_dq3_tx_de-skew = <8>; 216 cs1_dq4_rx_de-skew = <8>; 217 cs1_dq4_tx_de-skew = <8>; 218 cs1_dq5_rx_de-skew = <9>; 219 cs1_dq5_tx_de-skew = <8>; 220 cs1_dq6_rx_de-skew = <9>; 221 cs1_dq6_tx_de-skew = <8>; 222 cs1_dq7_rx_de-skew = <8>; 223 cs1_dq7_tx_de-skew = <8>; 224 cs1_dqs0_rx_de-skew = <6>; 225 cs1_dqs0p_tx_de-skew = <9>; 226 cs1_dqs0n_tx_de-skew = <9>; 227 228 cs1_dm1_rx_de-skew = <7>; 229 cs1_dm1_tx_de-skew = <7>; 230 cs1_dq8_rx_de-skew = <8>; 231 cs1_dq8_tx_de-skew = <8>; 232 cs1_dq9_rx_de-skew = <8>; 233 cs1_dq9_tx_de-skew = <7>; 234 cs1_dq10_rx_de-skew = <7>; 235 cs1_dq10_tx_de-skew = <8>; 236 cs1_dq11_rx_de-skew = <8>; 237 cs1_dq11_tx_de-skew = <8>; 238 cs1_dq12_rx_de-skew = <8>; 239 cs1_dq12_tx_de-skew = <7>; 240 cs1_dq13_rx_de-skew = <8>; 241 cs1_dq13_tx_de-skew = <8>; 242 cs1_dq14_rx_de-skew = <8>; 243 cs1_dq14_tx_de-skew = <8>; 244 cs1_dq15_rx_de-skew = <8>; 245 cs1_dq15_tx_de-skew = <7>; 246 cs1_dqs1_rx_de-skew = <7>; 247 cs1_dqs1p_tx_de-skew = <9>; 248 cs1_dqs1n_tx_de-skew = <9>; 249 250 cs1_dm2_rx_de-skew = <7>; 251 cs1_dm2_tx_de-skew = <8>; 252 cs1_dq16_rx_de-skew = <8>; 253 cs1_dq16_tx_de-skew = <9>; 254 cs1_dq17_rx_de-skew = <8>; 255 cs1_dq17_tx_de-skew = <9>; 256 cs1_dq18_rx_de-skew = <7>; 257 cs1_dq18_tx_de-skew = <8>; 258 cs1_dq19_rx_de-skew = <8>; 259 cs1_dq19_tx_de-skew = <9>; 260 cs1_dq20_rx_de-skew = <9>; 261 cs1_dq20_tx_de-skew = <9>; 262 cs1_dq21_rx_de-skew = <9>; 263 cs1_dq21_tx_de-skew = <9>; 264 cs1_dq22_rx_de-skew = <8>; 265 cs1_dq22_tx_de-skew = <9>; 266 cs1_dq23_rx_de-skew = <8>; 267 cs1_dq23_tx_de-skew = <9>; 268 cs1_dqs2_rx_de-skew = <6>; 269 cs1_dqs2p_tx_de-skew = <9>; 270 cs1_dqs2n_tx_de-skew = <9>; 271 272 cs1_dm3_rx_de-skew = <7>; 273 cs1_dm3_tx_de-skew = <7>; 274 cs1_dq24_rx_de-skew = <8>; 275 cs1_dq24_tx_de-skew = <9>; 276 cs1_dq25_rx_de-skew = <9>; 277 cs1_dq25_tx_de-skew = <9>; 278 cs1_dq26_rx_de-skew = <9>; 279 cs1_dq26_tx_de-skew = <8>; 280 cs1_dq27_rx_de-skew = <8>; 281 cs1_dq27_tx_de-skew = <8>; 282 cs1_dq28_rx_de-skew = <9>; 283 cs1_dq28_tx_de-skew = <9>; 284 cs1_dq29_rx_de-skew = <9>; 285 cs1_dq29_tx_de-skew = <9>; 286 cs1_dq30_rx_de-skew = <9>; 287 cs1_dq30_tx_de-skew = <8>; 288 cs1_dq31_rx_de-skew = <8>; 289 cs1_dq31_tx_de-skew = <8>; 290 cs1_dqs3_rx_de-skew = <7>; 291 cs1_dqs3p_tx_de-skew = <9>; 292 cs1_dqs3n_tx_de-skew = <9>; 293 }; 294}; 295