1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/clock/rockchip-ddr.h> 8#include <dt-bindings/memory/rk3328-dram.h> 9 10/ { 11 ddr_timing: ddr_timing { 12 compatible = "rockchip,ddr-timing"; 13 ddr3_speed_bin = <DDR3_DEFAULT>; 14 ddr4_speed_bin = <DDR4_DEFAULT>; 15 pd_idle = <0>; 16 sr_idle = <0>; 17 sr_mc_gate_idle = <0>; 18 srpd_lite_idle = <0>; 19 standby_idle = <0>; 20 21 auto_pd_dis_freq = <1066>; 22 auto_sr_dis_freq = <800>; 23 ddr3_dll_dis_freq = <300>; 24 ddr4_dll_dis_freq = <625>; 25 phy_dll_dis_freq = <400>; 26 27 ddr3_odt_dis_freq = <100>; 28 phy_ddr3_odt_dis_freq = <100>; 29 ddr3_drv = <DDR3_DS_40ohm>; 30 ddr3_odt = <DDR3_ODT_120ohm>; 31 phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>; 32 phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>; 33 phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>; 34 phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>; 35 36 lpddr3_odt_dis_freq = <666>; 37 phy_lpddr3_odt_dis_freq = <666>; 38 lpddr3_drv = <LP3_DS_40ohm>; 39 lpddr3_odt = <LP3_ODT_240ohm>; 40 phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>; 41 phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>; 42 phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>; 43 phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>; 44 45 lpddr4_odt_dis_freq = <800>; 46 phy_lpddr4_odt_dis_freq = <800>; 47 lpddr4_drv = <LP4_PDDS_60ohm>; 48 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; 49 lpddr4_ca_odt = <LP4_CA_ODT_40ohm>; 50 phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>; 51 phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>; 52 phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>; 53 phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>; 54 55 ddr4_odt_dis_freq = <666>; 56 phy_ddr4_odt_dis_freq = <666>; 57 ddr4_drv = <DDR4_DS_34ohm>; 58 ddr4_odt = <DDR4_RTT_NOM_240ohm>; 59 phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>; 60 phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>; 61 phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>; 62 phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>; 63 64 /* CA de-skew, one step is 47.8ps, range 0-15 */ 65 ddr3a1_ddr4a9_de-skew = <7>; 66 ddr3a0_ddr4a10_de-skew = <7>; 67 ddr3a3_ddr4a6_de-skew = <8>; 68 ddr3a2_ddr4a4_de-skew = <8>; 69 ddr3a5_ddr4a8_de-skew = <7>; 70 ddr3a4_ddr4a5_de-skew = <9>; 71 ddr3a7_ddr4a11_de-skew = <7>; 72 ddr3a6_ddr4a7_de-skew = <9>; 73 ddr3a9_ddr4a0_de-skew = <8>; 74 ddr3a8_ddr4a13_de-skew = <7>; 75 ddr3a11_ddr4a3_de-skew = <9>; 76 ddr3a10_ddr4cs0_de-skew = <7>; 77 ddr3a13_ddr4a2_de-skew = <8>; 78 ddr3a12_ddr4ba1_de-skew = <7>; 79 ddr3a15_ddr4odt0_de-skew = <7>; 80 ddr3a14_ddr4a1_de-skew = <8>; 81 ddr3ba1_ddr4a15_de-skew = <7>; 82 ddr3ba0_ddr4bg0_de-skew = <7>; 83 ddr3ras_ddr4cke_de-skew = <7>; 84 ddr3ba2_ddr4ba0_de-skew = <8>; 85 ddr3we_ddr4bg1_de-skew = <8>; 86 ddr3cas_ddr4a12_de-skew = <7>; 87 ddr3ckn_ddr4ckn_de-skew = <8>; 88 ddr3ckp_ddr4ckp_de-skew = <8>; 89 ddr3cke_ddr4a16_de-skew = <8>; 90 ddr3odt0_ddr4a14_de-skew = <7>; 91 ddr3cs0_ddr4act_de-skew = <8>; 92 ddr3reset_ddr4reset_de-skew = <7>; 93 ddr3cs1_ddr4cs1_de-skew = <7>; 94 ddr3odt1_ddr4odt1_de-skew = <7>; 95 96 /* DATA de-skew 97 * RX one step is 25.1ps, range 0-15 98 * TX one step is 47.8ps, range 0-15 99 */ 100 cs0_dm0_rx_de-skew = <7>; 101 cs0_dm0_tx_de-skew = <8>; 102 cs0_dq0_rx_de-skew = <7>; 103 cs0_dq0_tx_de-skew = <8>; 104 cs0_dq1_rx_de-skew = <7>; 105 cs0_dq1_tx_de-skew = <8>; 106 cs0_dq2_rx_de-skew = <7>; 107 cs0_dq2_tx_de-skew = <8>; 108 cs0_dq3_rx_de-skew = <7>; 109 cs0_dq3_tx_de-skew = <8>; 110 cs0_dq4_rx_de-skew = <7>; 111 cs0_dq4_tx_de-skew = <8>; 112 cs0_dq5_rx_de-skew = <7>; 113 cs0_dq5_tx_de-skew = <8>; 114 cs0_dq6_rx_de-skew = <7>; 115 cs0_dq6_tx_de-skew = <8>; 116 cs0_dq7_rx_de-skew = <7>; 117 cs0_dq7_tx_de-skew = <8>; 118 cs0_dqs0_rx_de-skew = <6>; 119 cs0_dqs0p_tx_de-skew = <9>; 120 cs0_dqs0n_tx_de-skew = <9>; 121 122 cs0_dm1_rx_de-skew = <7>; 123 cs0_dm1_tx_de-skew = <7>; 124 cs0_dq8_rx_de-skew = <7>; 125 cs0_dq8_tx_de-skew = <8>; 126 cs0_dq9_rx_de-skew = <7>; 127 cs0_dq9_tx_de-skew = <7>; 128 cs0_dq10_rx_de-skew = <7>; 129 cs0_dq10_tx_de-skew = <8>; 130 cs0_dq11_rx_de-skew = <7>; 131 cs0_dq11_tx_de-skew = <7>; 132 cs0_dq12_rx_de-skew = <7>; 133 cs0_dq12_tx_de-skew = <8>; 134 cs0_dq13_rx_de-skew = <7>; 135 cs0_dq13_tx_de-skew = <7>; 136 cs0_dq14_rx_de-skew = <7>; 137 cs0_dq14_tx_de-skew = <8>; 138 cs0_dq15_rx_de-skew = <7>; 139 cs0_dq15_tx_de-skew = <7>; 140 cs0_dqs1_rx_de-skew = <7>; 141 cs0_dqs1p_tx_de-skew = <9>; 142 cs0_dqs1n_tx_de-skew = <9>; 143 144 cs0_dm2_rx_de-skew = <7>; 145 cs0_dm2_tx_de-skew = <8>; 146 cs0_dq16_rx_de-skew = <7>; 147 cs0_dq16_tx_de-skew = <8>; 148 cs0_dq17_rx_de-skew = <7>; 149 cs0_dq17_tx_de-skew = <8>; 150 cs0_dq18_rx_de-skew = <7>; 151 cs0_dq18_tx_de-skew = <8>; 152 cs0_dq19_rx_de-skew = <7>; 153 cs0_dq19_tx_de-skew = <8>; 154 cs0_dq20_rx_de-skew = <7>; 155 cs0_dq20_tx_de-skew = <8>; 156 cs0_dq21_rx_de-skew = <7>; 157 cs0_dq21_tx_de-skew = <8>; 158 cs0_dq22_rx_de-skew = <7>; 159 cs0_dq22_tx_de-skew = <8>; 160 cs0_dq23_rx_de-skew = <7>; 161 cs0_dq23_tx_de-skew = <8>; 162 cs0_dqs2_rx_de-skew = <6>; 163 cs0_dqs2p_tx_de-skew = <9>; 164 cs0_dqs2n_tx_de-skew = <9>; 165 166 cs0_dm3_rx_de-skew = <7>; 167 cs0_dm3_tx_de-skew = <7>; 168 cs0_dq24_rx_de-skew = <7>; 169 cs0_dq24_tx_de-skew = <8>; 170 cs0_dq25_rx_de-skew = <7>; 171 cs0_dq25_tx_de-skew = <7>; 172 cs0_dq26_rx_de-skew = <7>; 173 cs0_dq26_tx_de-skew = <7>; 174 cs0_dq27_rx_de-skew = <7>; 175 cs0_dq27_tx_de-skew = <7>; 176 cs0_dq28_rx_de-skew = <7>; 177 cs0_dq28_tx_de-skew = <7>; 178 cs0_dq29_rx_de-skew = <7>; 179 cs0_dq29_tx_de-skew = <7>; 180 cs0_dq30_rx_de-skew = <7>; 181 cs0_dq30_tx_de-skew = <7>; 182 cs0_dq31_rx_de-skew = <7>; 183 cs0_dq31_tx_de-skew = <7>; 184 cs0_dqs3_rx_de-skew = <7>; 185 cs0_dqs3p_tx_de-skew = <9>; 186 cs0_dqs3n_tx_de-skew = <9>; 187 188 cs1_dm0_rx_de-skew = <7>; 189 cs1_dm0_tx_de-skew = <8>; 190 cs1_dq0_rx_de-skew = <7>; 191 cs1_dq0_tx_de-skew = <8>; 192 cs1_dq1_rx_de-skew = <7>; 193 cs1_dq1_tx_de-skew = <8>; 194 cs1_dq2_rx_de-skew = <7>; 195 cs1_dq2_tx_de-skew = <8>; 196 cs1_dq3_rx_de-skew = <7>; 197 cs1_dq3_tx_de-skew = <8>; 198 cs1_dq4_rx_de-skew = <7>; 199 cs1_dq4_tx_de-skew = <8>; 200 cs1_dq5_rx_de-skew = <7>; 201 cs1_dq5_tx_de-skew = <8>; 202 cs1_dq6_rx_de-skew = <7>; 203 cs1_dq6_tx_de-skew = <8>; 204 cs1_dq7_rx_de-skew = <7>; 205 cs1_dq7_tx_de-skew = <8>; 206 cs1_dqs0_rx_de-skew = <6>; 207 cs1_dqs0p_tx_de-skew = <9>; 208 cs1_dqs0n_tx_de-skew = <9>; 209 210 cs1_dm1_rx_de-skew = <7>; 211 cs1_dm1_tx_de-skew = <7>; 212 cs1_dq8_rx_de-skew = <7>; 213 cs1_dq8_tx_de-skew = <8>; 214 cs1_dq9_rx_de-skew = <7>; 215 cs1_dq9_tx_de-skew = <7>; 216 cs1_dq10_rx_de-skew = <7>; 217 cs1_dq10_tx_de-skew = <8>; 218 cs1_dq11_rx_de-skew = <7>; 219 cs1_dq11_tx_de-skew = <7>; 220 cs1_dq12_rx_de-skew = <7>; 221 cs1_dq12_tx_de-skew = <8>; 222 cs1_dq13_rx_de-skew = <7>; 223 cs1_dq13_tx_de-skew = <7>; 224 cs1_dq14_rx_de-skew = <7>; 225 cs1_dq14_tx_de-skew = <8>; 226 cs1_dq15_rx_de-skew = <7>; 227 cs1_dq15_tx_de-skew = <7>; 228 cs1_dqs1_rx_de-skew = <7>; 229 cs1_dqs1p_tx_de-skew = <9>; 230 cs1_dqs1n_tx_de-skew = <9>; 231 232 cs1_dm2_rx_de-skew = <7>; 233 cs1_dm2_tx_de-skew = <8>; 234 cs1_dq16_rx_de-skew = <7>; 235 cs1_dq16_tx_de-skew = <8>; 236 cs1_dq17_rx_de-skew = <7>; 237 cs1_dq17_tx_de-skew = <8>; 238 cs1_dq18_rx_de-skew = <7>; 239 cs1_dq18_tx_de-skew = <8>; 240 cs1_dq19_rx_de-skew = <7>; 241 cs1_dq19_tx_de-skew = <8>; 242 cs1_dq20_rx_de-skew = <7>; 243 cs1_dq20_tx_de-skew = <8>; 244 cs1_dq21_rx_de-skew = <7>; 245 cs1_dq21_tx_de-skew = <8>; 246 cs1_dq22_rx_de-skew = <7>; 247 cs1_dq22_tx_de-skew = <8>; 248 cs1_dq23_rx_de-skew = <7>; 249 cs1_dq23_tx_de-skew = <8>; 250 cs1_dqs2_rx_de-skew = <6>; 251 cs1_dqs2p_tx_de-skew = <9>; 252 cs1_dqs2n_tx_de-skew = <9>; 253 254 cs1_dm3_rx_de-skew = <7>; 255 cs1_dm3_tx_de-skew = <7>; 256 cs1_dq24_rx_de-skew = <7>; 257 cs1_dq24_tx_de-skew = <8>; 258 cs1_dq25_rx_de-skew = <7>; 259 cs1_dq25_tx_de-skew = <7>; 260 cs1_dq26_rx_de-skew = <7>; 261 cs1_dq26_tx_de-skew = <7>; 262 cs1_dq27_rx_de-skew = <7>; 263 cs1_dq27_tx_de-skew = <7>; 264 cs1_dq28_rx_de-skew = <7>; 265 cs1_dq28_tx_de-skew = <7>; 266 cs1_dq29_rx_de-skew = <7>; 267 cs1_dq29_tx_de-skew = <7>; 268 cs1_dq30_rx_de-skew = <7>; 269 cs1_dq30_tx_de-skew = <7>; 270 cs1_dq31_rx_de-skew = <7>; 271 cs1_dq31_tx_de-skew = <7>; 272 cs1_dqs3_rx_de-skew = <7>; 273 cs1_dqs3p_tx_de-skew = <9>; 274 cs1_dqs3n_tx_de-skew = <9>; 275 }; 276}; 277