1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rockchip-ddr.h> 7#include <dt-bindings/memory/rk1808-dram.h> 8 9/ { 10 ddr_timing: ddr_timing { 11 compatible = "rockchip,ddr-timing"; 12 ddr2_speed_bin = <DDR2_DEFAULT>; 13 ddr3_speed_bin = <DDR3_DEFAULT>; 14 ddr4_speed_bin = <DDR4_DEFAULT>; 15 pd_idle = <0>; 16 sr_idle = <0>; 17 sr_mc_gate_idle = <0>; 18 srpd_lite_idle = <0>; 19 standby_idle = <0>; 20 21 auto_pd_dis_freq = <1066>; 22 auto_sr_dis_freq = <800>; 23 ddr2_dll_dis_freq = <300>; 24 ddr3_dll_dis_freq = <300>; 25 ddr4_dll_dis_freq = <625>; 26 phy_dll_dis_freq = <400>; 27 28 ddr2_odt_dis_freq = <100>; 29 phy_ddr2_odt_dis_freq = <100>; 30 ddr2_drv = <DDR2_DS_REDUCE>; 31 ddr2_odt = <DDR2_ODT_150ohm>; 32 phy_ddr2_ca_drv = <PHY_DDR3_RON_34ohm>; 33 phy_ddr2_ck_drv = <PHY_DDR3_RON_43ohm>; 34 phy_ddr2_dq_drv = <PHY_DDR3_RON_34ohm>; 35 phy_ddr2_odt = <PHY_DDR3_RTT_213ohm>; 36 37 ddr3_odt_dis_freq = <400>; 38 phy_ddr3_odt_dis_freq = <400>; 39 ddr3_drv = <DDR3_DS_40ohm>; 40 ddr3_odt = <DDR3_ODT_120ohm>; 41 phy_ddr3_ca_drv = <PHY_DDR3_RON_34ohm>; 42 phy_ddr3_ck_drv = <PHY_DDR3_RON_43ohm>; 43 phy_ddr3_dq_drv = <PHY_DDR3_RON_34ohm>; 44 phy_ddr3_odt = <PHY_DDR3_RTT_213ohm>; 45 46 phy_lpddr2_odt_dis_freq = <666>; 47 lpddr2_drv = <LP2_DS_40ohm>; 48 phy_lpddr2_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>; 49 phy_lpddr2_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>; 50 phy_lpddr2_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>; 51 phy_lpddr2_odt = <PHY_DDR4_LPDDR2_3_RTT_DISABLE>; 52 53 lpddr3_odt_dis_freq = <400>; 54 phy_lpddr3_odt_dis_freq = <400>; 55 lpddr3_drv = <LP3_DS_40ohm>; 56 lpddr3_odt = <LP3_ODT_240ohm>; 57 phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>; 58 phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>; 59 phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>; 60 phy_lpddr3_odt = <PHY_DDR4_LPDDR2_3_RTT_229ohm>; 61 62 lpddr4_odt_dis_freq = <800>; 63 phy_lpddr4_odt_dis_freq = <800>; 64 lpddr4_drv = <LP4_PDDS_60ohm>; 65 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; 66 lpddr4_ca_odt = <LP4_CA_ODT_40ohm>; 67 phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>; 68 phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR2_3_RON_75ohm>; 69 phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR2_3_RON_75ohm>; 70 phy_lpddr4_odt = <PHY_DDR4_LPDDR2_3_RTT_54ohm>; 71 72 ddr4_odt_dis_freq = <666>; 73 phy_ddr4_odt_dis_freq = <666>; 74 ddr4_drv = <DDR4_DS_34ohm>; 75 ddr4_odt = <DDR4_RTT_NOM_240ohm>; 76 phy_ddr4_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>; 77 phy_ddr4_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>; 78 phy_ddr4_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>; 79 phy_ddr4_odt = <PHY_DDR4_LPDDR2_3_RTT_229ohm>; 80 81 /* 82 * CA de-skew, one step is 15ps, range 0-31 83 * DDR3 CA define is different from others(DDR4/LPDDR2/LPDDR3). 84 */ 85 a0_ddr3a9_de-skew = <7>; 86 a1_ddr3a14_de-skew = <7>; 87 a2_ddr3a13_de-skew = <7>; 88 a3_ddr3a11_de-skew = <7>; 89 a4_ddr3a2_de-skew = <7>; 90 a5_ddr3a4_de-skew = <7>; 91 a6_ddr3a3_de-skew = <7>; 92 a7_ddr3a6_de-skew = <7>; 93 a8_ddr3a5_de-skew = <7>; 94 a9_ddr3a1_de-skew = <7>; 95 a10_ddr3a0_de-skew = <7>; 96 a11_ddr3a7_de-skew = <7>; 97 a12_ddr3casb_de-skew = <7>; 98 a13_ddr3a8_de-skew = <7>; 99 a14_ddr3odt0_de-skew = <7>; 100 a15_ddr3ba1_de-skew = <7>; 101 a16_ddr3rasb_de-skew = <7>; 102 a17_ddr3null_de-skew = <7>; 103 ba0_ddr3ba2_de-skew = <7>; 104 ba1_ddr3a12_de-skew = <7>; 105 bg0_ddr3ba0_de-skew = <7>; 106 bg1_ddr3web_de-skew = <7>; 107 cke_ddr3cke_de-skew = <7>; 108 ck_ddr3ck_de-skew = <7>; 109 ckb_ddr3ckb_de-skew = <7>; 110 csb0_ddr3a10_de-skew = <7>; 111 odt0_ddr3a15_de-skew = <7>; 112 resetn_ddr3resetn_de-skew = <7>; 113 actn_ddr3csb0_de-skew = <7>; 114 csb1_ddr3csb1_de-skew = <7>; 115 odt1_ddr3odt1_de-skew = <7>; 116 117 /* DATA de-skew, one step is 15ps, range 0-31 */ 118 /* cs0_skew_a */ 119 cs0_dm0_rx_de-skew = <7>; 120 cs0_dm0_tx_de-skew = <7>; 121 cs0_dq0_rx_de-skew = <7>; 122 cs0_dq0_tx_de-skew = <7>; 123 cs0_dq1_rx_de-skew = <7>; 124 cs0_dq1_tx_de-skew = <7>; 125 cs0_dq2_rx_de-skew = <7>; 126 cs0_dq2_tx_de-skew = <7>; 127 cs0_dq3_rx_de-skew = <7>; 128 cs0_dq3_tx_de-skew = <7>; 129 cs0_dq4_rx_de-skew = <7>; 130 cs0_dq4_tx_de-skew = <7>; 131 cs0_dq5_rx_de-skew = <7>; 132 cs0_dq5_tx_de-skew = <7>; 133 cs0_dq6_rx_de-skew = <7>; 134 cs0_dq6_tx_de-skew = <7>; 135 cs0_dq7_rx_de-skew = <7>; 136 cs0_dq7_tx_de-skew = <7>; 137 cs0_dqs0p_rx_de-skew = <14>; 138 cs0_dqs0p_tx_de-skew = <9>; 139 cs0_dqs0n_tx_de-skew = <9>; 140 cs0_dm1_rx_de-skew = <7>; 141 cs0_dm1_tx_de-skew = <7>; 142 cs0_dq8_rx_de-skew = <7>; 143 cs0_dq8_tx_de-skew = <7>; 144 cs0_dq9_rx_de-skew = <7>; 145 cs0_dq9_tx_de-skew = <7>; 146 cs0_dq10_rx_de-skew = <7>; 147 cs0_dq10_tx_de-skew = <7>; 148 cs0_dq11_rx_de-skew = <7>; 149 cs0_dq11_tx_de-skew = <7>; 150 cs0_dq12_rx_de-skew = <7>; 151 cs0_dq12_tx_de-skew = <7>; 152 cs0_dq13_rx_de-skew = <7>; 153 cs0_dq13_tx_de-skew = <7>; 154 cs0_dq14_rx_de-skew = <7>; 155 cs0_dq14_tx_de-skew = <7>; 156 cs0_dq15_rx_de-skew = <7>; 157 cs0_dq15_tx_de-skew = <7>; 158 cs0_dqs1p_rx_de-skew = <14>; 159 cs0_dqs1p_tx_de-skew = <9>; 160 cs0_dqs1n_tx_de-skew = <9>; 161 cs0_dqs0n_rx_de-skew = <14>; 162 cs0_dqs1n_rx_de-skew = <14>; 163 164 /* cs0_skew_b */ 165 cs0_dm2_rx_de-skew = <7>; 166 cs0_dm2_tx_de-skew = <7>; 167 cs0_dq16_rx_de-skew = <7>; 168 cs0_dq16_tx_de-skew = <7>; 169 cs0_dq17_rx_de-skew = <7>; 170 cs0_dq17_tx_de-skew = <7>; 171 cs0_dq18_rx_de-skew = <7>; 172 cs0_dq18_tx_de-skew = <7>; 173 cs0_dq19_rx_de-skew = <7>; 174 cs0_dq19_tx_de-skew = <7>; 175 cs0_dq20_rx_de-skew = <7>; 176 cs0_dq20_tx_de-skew = <7>; 177 cs0_dq21_rx_de-skew = <7>; 178 cs0_dq21_tx_de-skew = <7>; 179 cs0_dq22_rx_de-skew = <7>; 180 cs0_dq22_tx_de-skew = <7>; 181 cs0_dq23_rx_de-skew = <7>; 182 cs0_dq23_tx_de-skew = <7>; 183 cs0_dqs2p_rx_de-skew = <14>; 184 cs0_dqs2p_tx_de-skew = <9>; 185 cs0_dqs2n_tx_de-skew = <9>; 186 cs0_dm3_rx_de-skew = <7>; 187 cs0_dm3_tx_de-skew = <7>; 188 cs0_dq24_rx_de-skew = <7>; 189 cs0_dq24_tx_de-skew = <7>; 190 cs0_dq25_rx_de-skew = <7>; 191 cs0_dq25_tx_de-skew = <7>; 192 cs0_dq26_rx_de-skew = <7>; 193 cs0_dq26_tx_de-skew = <7>; 194 cs0_dq27_rx_de-skew = <7>; 195 cs0_dq27_tx_de-skew = <7>; 196 cs0_dq28_rx_de-skew = <7>; 197 cs0_dq28_tx_de-skew = <7>; 198 cs0_dq29_rx_de-skew = <7>; 199 cs0_dq29_tx_de-skew = <7>; 200 cs0_dq30_rx_de-skew = <7>; 201 cs0_dq30_tx_de-skew = <7>; 202 cs0_dq31_rx_de-skew = <7>; 203 cs0_dq31_tx_de-skew = <7>; 204 cs0_dqs3p_rx_de-skew = <14>; 205 cs0_dqs3p_tx_de-skew = <9>; 206 cs0_dqs3n_tx_de-skew = <9>; 207 cs0_dqs2n_rx_de-skew = <14>; 208 cs0_dqs3n_rx_de-skew = <14>; 209 210 /* cs1_skew_a */ 211 cs1_dm0_rx_de-skew = <7>; 212 cs1_dm0_tx_de-skew = <7>; 213 cs1_dq0_rx_de-skew = <7>; 214 cs1_dq0_tx_de-skew = <7>; 215 cs1_dq1_rx_de-skew = <7>; 216 cs1_dq1_tx_de-skew = <7>; 217 cs1_dq2_rx_de-skew = <7>; 218 cs1_dq2_tx_de-skew = <7>; 219 cs1_dq3_rx_de-skew = <7>; 220 cs1_dq3_tx_de-skew = <7>; 221 cs1_dq4_rx_de-skew = <7>; 222 cs1_dq4_tx_de-skew = <7>; 223 cs1_dq5_rx_de-skew = <7>; 224 cs1_dq5_tx_de-skew = <7>; 225 cs1_dq6_rx_de-skew = <7>; 226 cs1_dq6_tx_de-skew = <7>; 227 cs1_dq7_rx_de-skew = <7>; 228 cs1_dq7_tx_de-skew = <7>; 229 cs1_dqs0p_rx_de-skew = <14>; 230 cs1_dqs0p_tx_de-skew = <9>; 231 cs1_dqs0n_tx_de-skew = <9>; 232 cs1_dm1_rx_de-skew = <7>; 233 cs1_dm1_tx_de-skew = <7>; 234 cs1_dq8_rx_de-skew = <7>; 235 cs1_dq8_tx_de-skew = <7>; 236 cs1_dq9_rx_de-skew = <7>; 237 cs1_dq9_tx_de-skew = <7>; 238 cs1_dq10_rx_de-skew = <7>; 239 cs1_dq10_tx_de-skew = <7>; 240 cs1_dq11_rx_de-skew = <7>; 241 cs1_dq11_tx_de-skew = <7>; 242 cs1_dq12_rx_de-skew = <7>; 243 cs1_dq12_tx_de-skew = <7>; 244 cs1_dq13_rx_de-skew = <7>; 245 cs1_dq13_tx_de-skew = <7>; 246 cs1_dq14_rx_de-skew = <7>; 247 cs1_dq14_tx_de-skew = <7>; 248 cs1_dq15_rx_de-skew = <7>; 249 cs1_dq15_tx_de-skew = <7>; 250 cs1_dqs1p_rx_de-skew = <14>; 251 cs1_dqs1p_tx_de-skew = <9>; 252 cs1_dqs1n_tx_de-skew = <9>; 253 cs1_dqs0n_rx_de-skew = <14>; 254 cs1_dqs1n_rx_de-skew = <14>; 255 256 /* cs1_skew_b */ 257 cs1_dm2_rx_de-skew = <7>; 258 cs1_dm2_tx_de-skew = <7>; 259 cs1_dq16_rx_de-skew = <7>; 260 cs1_dq16_tx_de-skew = <7>; 261 cs1_dq17_rx_de-skew = <7>; 262 cs1_dq17_tx_de-skew = <7>; 263 cs1_dq18_rx_de-skew = <7>; 264 cs1_dq18_tx_de-skew = <7>; 265 cs1_dq19_rx_de-skew = <7>; 266 cs1_dq19_tx_de-skew = <7>; 267 cs1_dq20_rx_de-skew = <7>; 268 cs1_dq20_tx_de-skew = <7>; 269 cs1_dq21_rx_de-skew = <7>; 270 cs1_dq21_tx_de-skew = <7>; 271 cs1_dq22_rx_de-skew = <7>; 272 cs1_dq22_tx_de-skew = <7>; 273 cs1_dq23_rx_de-skew = <7>; 274 cs1_dq23_tx_de-skew = <7>; 275 cs1_dqs2p_rx_de-skew = <14>; 276 cs1_dqs2p_tx_de-skew = <9>; 277 cs1_dqs2n_tx_de-skew = <9>; 278 cs1_dm3_rx_de-skew = <7>; 279 cs1_dm3_tx_de-skew = <7>; 280 cs1_dq24_rx_de-skew = <7>; 281 cs1_dq24_tx_de-skew = <7>; 282 cs1_dq25_rx_de-skew = <7>; 283 cs1_dq25_tx_de-skew = <7>; 284 cs1_dq26_rx_de-skew = <7>; 285 cs1_dq26_tx_de-skew = <7>; 286 cs1_dq27_rx_de-skew = <7>; 287 cs1_dq27_tx_de-skew = <7>; 288 cs1_dq28_rx_de-skew = <7>; 289 cs1_dq28_tx_de-skew = <7>; 290 cs1_dq29_rx_de-skew = <7>; 291 cs1_dq29_tx_de-skew = <7>; 292 cs1_dq30_rx_de-skew = <7>; 293 cs1_dq30_tx_de-skew = <7>; 294 cs1_dq31_rx_de-skew = <7>; 295 cs1_dq31_tx_de-skew = <7>; 296 cs1_dqs3p_rx_de-skew = <14>; 297 cs1_dqs3p_tx_de-skew = <9>; 298 cs1_dqs3n_tx_de-skew = <9>; 299 cs1_dqs2n_rx_de-skew = <14>; 300 cs1_dqs3n_rx_de-skew = <14>; 301 }; 302}; 303