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/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/
H A Duncore-ddrc.json5 "BriefDescription": "DDRC total write operations",
6 "PublicDescription": "DDRC total write operations",
7 "Unit": "hisi_sccl,ddrc"
12 "BriefDescription": "DDRC total read operations",
13 "PublicDescription": "DDRC total read operations",
14 "Unit": "hisi_sccl,ddrc"
19 "BriefDescription": "DDRC write commands",
20 "PublicDescription": "DDRC write commands",
21 "Unit": "hisi_sccl,ddrc"
26 "BriefDescription": "DDRC read commands",
[all …]
H A Duncore-hha.json33 "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
34 "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
40 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
41 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
47 … "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
48 … "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
54 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
55 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
20 The Linux driver for the DDRC doesn't even map registers (they're included
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
63 ddrc: memory-controller@3d400000 {
[all …]
/OK3568_Linux_fs/kernel/drivers/perf/hisilicon/
H A Dhisi_uncore_ddrc_pmu.c3 * HiSilicon SoC DDRC uncore Hardware event counters support
22 /* DDRC register definition */
37 /* DDRC has 8-counters */
42 * For DDRC PMU, there are eight-events and every event has been mapped
56 * In DDRC there are no programmable counter, the count
93 * For DDRC PMU, event has been mapped to fixed-purpose counter by hardware,
148 /* For DDRC PMU, we use event code as counter index */ in hisi_ddrc_pmu_get_event_idx()
247 * Use the SCCL_ID and DDRC channel ID to identify the in hisi_ddrc_pmu_init_data()
248 * DDRC PMU, while SCCL_ID is in MPIDR[aff2]. in hisi_ddrc_pmu_init_data()
252 dev_err(&pdev->dev, "Can not read ddrc channel-id!\n"); in hisi_ddrc_pmu_init_data()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dsynopsys.txt14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
18 Required properties for "xlnx,zynqmp-ddrc-2.40a":
23 compatible = "xlnx,zynq-ddrc-a05";
28 compatible = "xlnx,zynqmp-ddrc-2.40a";
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interconnect/
H A Dfsl,imx8m-noc.yaml50 fsl,ddrc:
78 fsl,ddrc = <&ddrc>;
93 ddrc: memory-controller@3d400000 {
94 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
/OK3568_Linux_fs/u-boot/board/atmel/sama5d2_ptc/
H A Dsama5d2_ptc.c208 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
210 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
212 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
221 ddrc->rtr = 0x511; in ddrc_conf()
223 ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | in ddrc_conf()
232 ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | in ddrc_conf()
237 ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | in ddrc_conf()
/OK3568_Linux_fs/u-boot/board/atmel/sama5d2_xplained/
H A Dsama5d2_xplained.c219 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
221 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
223 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
232 ddrc->rtr = 0x511; in ddrc_conf()
234 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddrc_conf()
243 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | in ddrc_conf()
248 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | in ddrc_conf()
/OK3568_Linux_fs/kernel/Documentation/admin-guide/perf/
H A Dhisi-pmu.rst6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
20 HHA and DDRC etc. The available events and configuration options shall
23 /sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
24 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/test/test_cpu/
H A Duncore.json5 "BriefDescription": "DDRC write commands",
6 "PublicDescription": "DDRC write commands",
7 "Unit": "hisi_sccl,ddrc"
/OK3568_Linux_fs/kernel/arch/arm/mach-zynq/
H A Dpm.c58 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()
60 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); in zynq_pm_late_init()
63 * Enable DDRC clock stop feature. The HW takes care of in zynq_pm_late_init()
/OK3568_Linux_fs/kernel/drivers/devfreq/
H A Dimx8m-ddrc.c262 dev_err(dev, "ddrc failed freq switch to %lu from %lu: error %d. now at %lu\n", in imx8m_ddrc_target()
265 dev_err(dev, "ddrc failed freq update to %lu from %lu, now at %lu\n", in imx8m_ddrc_target()
268 dev_dbg(dev, "ddrc freq set to %lu (was %lu)\n", in imx8m_ddrc_target()
455 { .compatible = "fsl,imx8m-ddrc", },
463 .name = "imx8m-ddrc-devfreq",
H A DMakefile13 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dsoc.c295 /* disables propagation of barrier transactions to DDRC from CCI400 */ in erratum_a008850_early()
298 /* disable the re-ordering in DDRC */ in erratum_a008850_early()
315 /* enable propagation of barrier transactions to DDRC from CCI400 */ in erratum_a008850_post()
318 /* enable the re-ordering in DDRC */ in erratum_a008850_post()
/OK3568_Linux_fs/kernel/tools/perf/tests/
H A Dpmu-events.c93 .desc = "DDRC write commands. Unit: hisi_sccl,ddrc ",
95 .long_desc = "DDRC write commands",
96 .pmu = "hisi_sccl,ddrc",
99 .alias_long_desc = "DDRC write commands",
/OK3568_Linux_fs/u-boot/arch/arm/mach-zynq/
H A DMakefile13 obj-y += ddrc.o
H A DKconfig31 bool "Zynq DDRC initialization"
/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspd_sdram.c185 /* Check if the number of row of the module is in the range of DDRC */ in spd_sdram()
187 printf("DDR: Row number is out of range of DDRC, row=%02X\n", in spd_sdram()
192 /* Check if the number of col of the module is in the range of DDRC */ in spd_sdram()
194 printf("DDR: Col number is out of range of DDRC, col=%02X\n", in spd_sdram()
826 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); in spd_sdram()
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mm-evk.dts20 &ddrc {
/OK3568_Linux_fs/kernel/drivers/interconnect/imx/
H A Dimx8mn.c17 .phandle_name = "fsl,ddrc",
H A Dimx8mq.c18 .phandle_name = "fsl,ddrc",
H A Dimx8mm.c20 .phandle_name = "fsl,ddrc",
/OK3568_Linux_fs/u-boot/board/hisilicon/hikey/
H A DREADME123 INFO: lpddr3_freq_init, set ddrc 533mhz
126 INFO: lpddr3_freq_init, set ddrc 800mhz
/OK3568_Linux_fs/kernel/drivers/edac/
H A Dsynopsys_edac.c207 /* DDRC Software control register */
210 /* DDRC ECC CE & UE poison mask */
214 /* DDRC Device config masks */
901 .compatible = "xlnx,zynq-ddrc-a05",
905 .compatible = "xlnx,zynqmp-ddrc-2.40a",
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-rc32434/
H A Dddr.h40 u32 ddrc; member

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