1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Interconnect framework driver for i.MX8MQ SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2019-2020, NXP
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/interconnect-provider.h>
11*4882a593Smuzhiyun #include <dt-bindings/interconnect/imx8mq.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "imx.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const struct imx_icc_node_adj_desc imx8mq_dram_adj = {
16*4882a593Smuzhiyun .bw_mul = 1,
17*4882a593Smuzhiyun .bw_div = 4,
18*4882a593Smuzhiyun .phandle_name = "fsl,ddrc",
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static const struct imx_icc_node_adj_desc imx8mq_noc_adj = {
22*4882a593Smuzhiyun .bw_mul = 1,
23*4882a593Smuzhiyun .bw_div = 4,
24*4882a593Smuzhiyun .main_noc = true,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * Describe bus masters, slaves and connections between them
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * This is a simplified subset of the bus diagram, there are several other
31*4882a593Smuzhiyun * PL301 nics which are skipped/merged into PL301_MAIN
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun static struct imx_icc_node_desc nodes[] = {
34*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("NOC", IMX8MQ_ICN_NOC, &imx8mq_noc_adj,
35*4882a593Smuzhiyun IMX8MQ_ICS_DRAM, IMX8MQ_ICN_MAIN),
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun DEFINE_BUS_SLAVE("DRAM", IMX8MQ_ICS_DRAM, &imx8mq_dram_adj),
38*4882a593Smuzhiyun DEFINE_BUS_SLAVE("OCRAM", IMX8MQ_ICS_OCRAM, NULL),
39*4882a593Smuzhiyun DEFINE_BUS_MASTER("A53", IMX8MQ_ICM_A53, IMX8MQ_ICN_NOC),
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* VPUMIX */
42*4882a593Smuzhiyun DEFINE_BUS_MASTER("VPU", IMX8MQ_ICM_VPU, IMX8MQ_ICN_VIDEO),
43*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MQ_ICN_VIDEO, NULL, IMX8MQ_ICN_NOC),
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* GPUMIX */
46*4882a593Smuzhiyun DEFINE_BUS_MASTER("GPU", IMX8MQ_ICM_GPU, IMX8MQ_ICN_GPU),
47*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MQ_ICN_GPU, NULL, IMX8MQ_ICN_NOC),
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* DISPMIX (only for DCSS) */
50*4882a593Smuzhiyun DEFINE_BUS_MASTER("DC", IMX8MQ_ICM_DCSS, IMX8MQ_ICN_DCSS),
51*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_DC", IMX8MQ_ICN_DCSS, NULL, IMX8MQ_ICN_NOC),
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* USBMIX */
54*4882a593Smuzhiyun DEFINE_BUS_MASTER("USB1", IMX8MQ_ICM_USB1, IMX8MQ_ICN_USB),
55*4882a593Smuzhiyun DEFINE_BUS_MASTER("USB2", IMX8MQ_ICM_USB2, IMX8MQ_ICN_USB),
56*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_USB", IMX8MQ_ICN_USB, NULL, IMX8MQ_ICN_NOC),
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* PL301_DISPLAY (IPs other than DCSS, inside SUPERMIX) */
59*4882a593Smuzhiyun DEFINE_BUS_MASTER("CSI1", IMX8MQ_ICM_CSI1, IMX8MQ_ICN_DISPLAY),
60*4882a593Smuzhiyun DEFINE_BUS_MASTER("CSI2", IMX8MQ_ICM_CSI2, IMX8MQ_ICN_DISPLAY),
61*4882a593Smuzhiyun DEFINE_BUS_MASTER("LCDIF", IMX8MQ_ICM_LCDIF, IMX8MQ_ICN_DISPLAY),
62*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_DISPLAY", IMX8MQ_ICN_DISPLAY, NULL, IMX8MQ_ICN_MAIN),
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* AUDIO */
65*4882a593Smuzhiyun DEFINE_BUS_MASTER("SDMA2", IMX8MQ_ICM_SDMA2, IMX8MQ_ICN_AUDIO),
66*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MQ_ICN_AUDIO, NULL, IMX8MQ_ICN_DISPLAY),
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* ENET */
69*4882a593Smuzhiyun DEFINE_BUS_MASTER("ENET", IMX8MQ_ICM_ENET, IMX8MQ_ICN_ENET),
70*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MQ_ICN_ENET, NULL, IMX8MQ_ICN_MAIN),
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* OTHER */
73*4882a593Smuzhiyun DEFINE_BUS_MASTER("SDMA1", IMX8MQ_ICM_SDMA1, IMX8MQ_ICN_MAIN),
74*4882a593Smuzhiyun DEFINE_BUS_MASTER("NAND", IMX8MQ_ICM_NAND, IMX8MQ_ICN_MAIN),
75*4882a593Smuzhiyun DEFINE_BUS_MASTER("USDHC1", IMX8MQ_ICM_USDHC1, IMX8MQ_ICN_MAIN),
76*4882a593Smuzhiyun DEFINE_BUS_MASTER("USDHC2", IMX8MQ_ICM_USDHC2, IMX8MQ_ICN_MAIN),
77*4882a593Smuzhiyun DEFINE_BUS_MASTER("PCIE1", IMX8MQ_ICM_PCIE1, IMX8MQ_ICN_MAIN),
78*4882a593Smuzhiyun DEFINE_BUS_MASTER("PCIE2", IMX8MQ_ICM_PCIE2, IMX8MQ_ICN_MAIN),
79*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MQ_ICN_MAIN, NULL,
80*4882a593Smuzhiyun IMX8MQ_ICN_NOC, IMX8MQ_ICS_OCRAM),
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
imx8mq_icc_probe(struct platform_device * pdev)83*4882a593Smuzhiyun static int imx8mq_icc_probe(struct platform_device *pdev)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes));
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
imx8mq_icc_remove(struct platform_device * pdev)88*4882a593Smuzhiyun static int imx8mq_icc_remove(struct platform_device *pdev)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun return imx_icc_unregister(pdev);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static struct platform_driver imx8mq_icc_driver = {
94*4882a593Smuzhiyun .probe = imx8mq_icc_probe,
95*4882a593Smuzhiyun .remove = imx8mq_icc_remove,
96*4882a593Smuzhiyun .driver = {
97*4882a593Smuzhiyun .name = "imx8mq-interconnect",
98*4882a593Smuzhiyun .sync_state = icc_sync_state,
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun module_platform_driver(imx8mq_icc_driver);
103*4882a593Smuzhiyun MODULE_ALIAS("platform:imx8mq-interconnect");
104*4882a593Smuzhiyun MODULE_AUTHOR("Leonard Crestez <leonard.crestez@nxp.com>");
105*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
106