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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for DRA7xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM43xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
12 ti,bit-shift = <31>;
17 #clock-cells = <0>;
18 compatible = "ti,mux-clock";
20 ti,bit-shift = <29>;
25 #clock-cells = <0>;
26 compatible = "ti,mux-clock";
[all …]
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
12 ti,bit-shift = <22>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <1>;
25 #clock-cells = <0>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <12000000>;
15 #clock-cells = <0>;
16 compatible = "ti,gate-clock";
18 ti,bit-shift = <8>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <59000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <12000000>;
21 #clock-cells = <0>;
22 compatible = "ti,gate-clock";
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-no-wait-gate-clock";
12 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-divider-clock";
20 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dam33xx-clocks.dtsi2 * Device Tree Source for AM33xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
15 ti,bit-shift = <22>;
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
[all …]
H A Dam43xx-clocks.dtsi2 * Device Tree Source for AM43xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
15 ti,bit-shift = <31>;
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
23 ti,bit-shift = <29>;
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
31 ti,bit-shift = <22>;
[all …]
H A Ddra7xx-clocks.dtsi2 * Device Tree Source for DRA7xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
[all …]
H A Domap3xxx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
28 ti,bit-shift = <6>;
29 ti,max-div = <3>;
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP34xx/OMAP36xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,composite-no-wait-gate-clock";
15 ti,bit-shift = <0>;
20 #clock-cells = <0>;
21 compatible = "ti,composite-divider-clock";
23 ti,bit-shift = <8>;
29 #clock-cells = <0>;
30 compatible = "ti,composite-clock";
35 #clock-cells = <0>;
[all …]
H A Dkeystone-clocks.dtsi2 * Device Tree Source for Keystone 2 clock tree
12 #address-cells = <1>;
13 #size-cells = <1>;
17 #clock-cells = <0>;
18 compatible = "ti,keystone,pll-mux-clock";
21 bit-shift = <23>;
22 bit-mask = <1>;
23 clock-output-names = "mainmuxclk";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
32 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
63 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
67 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
[all …]
H A Dclk-div6.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_shift: Shift to access the register bits to select the parent clock
32 * @src_width: Number of register bits to select the parent clock (may be 0)
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/zynqmp/
H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
18 * Traits of this clock:
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c4 * SPDX-License-Identifier: GPL-2.0+
9 * bcm235xx architecture clock framework
18 #include <asm/kona-common/clk.h>
19 #include "clk-core.h"
22 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
41 return -EINVAL; in clk_get_and_enable()
74 return -ETIMEDOUT; in wait_bit()
77 /* Enable a peripheral clock */
83 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
84 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c4 * SPDX-License-Identifier: GPL-2.0+
9 * bcm281xx architecture clock framework
18 #include <asm/kona-common/clk.h>
19 #include "clk-core.h"
22 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
41 return -EINVAL; in clk_get_and_enable()
74 return -ETIMEDOUT; in wait_bit()
77 /* Enable a peripheral clock */
83 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
84 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/berlin/
H A Dberlin2-div.c1 // SPDX-License-Identifier: GPL-2.0
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
9 #include <linux/clk-provider.h>
16 #include "berlin2-div.h"
19 * Clock dividers in Berlin2 SoCs comprise a complex cell to select
23 * +---+
24 * pll0 --------------->| 0 | +---+
25 * +---+ |(B)|--+--------------->| 0 | +---+
26 * pll1.0 -->| 0 | +-->| 1 | | +--------+ |(E)|----->| 0 | +---+
27 * pll1.1 -->| 1 | | +---+ +-->|(C) 1:M |-->| 1 | |(F)|-->|(G)|->
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-divider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Adjustable divider clock implementation
10 #include <linux/clk-provider.h>
19 * DOC: basic adjustable divider clock that cannot gate
21 * Traits of this clock:
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
25 * parent - fixed parent. No clk_set_parent support
[all …]
H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-kona-setup.c18 #include "clk-kona.h"
21 #define selector_clear_exists(sel) ((sel)->width = 0)
28 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
31 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
34 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
37 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
40 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
43 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
53 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
55 struct bcm_clk_div *div; in clk_requires_trigger() local
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-clock.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/clock/bcm-sr.h>
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 #clock-cells = <0>;
43 compatible = "fixed-factor-clock";
45 clock-div = <2>;
46 clock-mult = <1>;
50 #clock-cells = <1>;
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Daptina-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "aptina-pll.h"
25 unsigned int div; in aptina_pll_calculate() local
27 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
28 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
30 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
31 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
32 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
33 return -EINVAL; in aptina_pll_calculate()
36 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
[all …]

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