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Searched full:mclk (Results 1 – 25 of 1219) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclk-hi3620.c284 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_determine_rate() local
286 if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) { in mmc_clk_determine_rate()
323 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_set_timing() local
360 val = readl_relaxed(mclk->clken_reg); in mmc_clk_set_timing()
361 val &= ~(1 << mclk->clken_bit); in mmc_clk_set_timing()
362 writel_relaxed(val, mclk->clken_reg); in mmc_clk_set_timing()
364 val = readl_relaxed(mclk->sam_reg); in mmc_clk_set_timing()
365 val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits); in mmc_clk_set_timing()
366 writel_relaxed(val, mclk->sam_reg); in mmc_clk_set_timing()
368 val = readl_relaxed(mclk->drv_reg); in mmc_clk_set_timing()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Ddummy-codec.c19 struct clk *mclk; member
27 if (!IS_ERR(dcp->mclk)) in dummy_codec_startup()
28 clk_prepare_enable(dcp->mclk); in dummy_codec_startup()
38 if (!IS_ERR(dcp->mclk)) in dummy_codec_shutdown()
39 clk_disable_unprepare(dcp->mclk); in dummy_codec_shutdown()
86 /* optional mclk, if needs, assign mclk in dts node */ in rockchip_dummy_codec_probe()
87 dcp->mclk = devm_clk_get(&pdev->dev, "mclk"); in rockchip_dummy_codec_probe()
88 if (IS_ERR(dcp->mclk)) { in rockchip_dummy_codec_probe()
89 if (PTR_ERR(dcp->mclk) == -EPROBE_DEFER) in rockchip_dummy_codec_probe()
91 else if (PTR_ERR(dcp->mclk) != -ENOENT) in rockchip_dummy_codec_probe()
H A Dcx20810_config.h30 * 12.288Mhz MClk, bclk,48K* 64 , 3.072Mhz
31 * set up PLL, 12.288 Mhz mclk feed to PLL
34 0x80, 0x03, /* MCLK is an input */
35 0x08, 0x20, /* MCLK !gated */
146 0x80, 0x03, /* MCLK */
156 0x08, 0x00, /* disable MCLK to chip */
161 /* enable MCLK to chip */
227 0x80, 0x03, /* MCLK */
235 0x08, 0x00, /* disable MCLK */
267 0x08, 0x00, /* disable MCLK to chip */
[all …]
H A Dwm8731.c46 struct clk *mclk; member
249 u32 mclk; member
257 /* codec mclk clock divider coefficients */
322 static inline int get_coeff(int mclk, int rate) in get_coeff() argument
327 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) in get_coeff()
391 if (wm8731->mclk && clk_set_rate(wm8731->mclk, freq)) in wm8731_set_dai_sysclk()
494 if (wm8731->mclk) { in wm8731_set_bias_level()
495 ret = clk_prepare_enable(wm8731->mclk); in wm8731_set_bias_level()
517 if (wm8731->mclk) in wm8731_set_bias_level()
518 clk_disable_unprepare(wm8731->mclk); in wm8731_set_bias_level()
[all …]
H A Dcs4234.c36 struct clk *mclk; member
371 dev_err(component->dev, "Unsupported mclk/lrclk rate\n"); in cs4234_dai_hw_params()
427 /* Scale MCLK rate by 64 to avoid overflow in the ratnum calculation */
448 int mclk = cs4234->mclk_rate; in cs4234_dai_rule_rate() local
451 .min = mclk / clamp(mclk / 30000, 256, 512), in cs4234_dai_rule_rate()
452 .max = mclk / clamp(mclk / 50000, 256, 512), in cs4234_dai_rule_rate()
455 .min = mclk / clamp(mclk / 60000, 128, 256), in cs4234_dai_rule_rate()
456 .max = mclk / clamp(mclk / 100000, 128, 256), in cs4234_dai_rule_rate()
515 * MCLK/rate may be a valid ratio but out-of-spec (e.g. 24576000/64000) in cs4234_dai_startup()
516 * so this rule limits the range of sample rate for given MCLK. in cs4234_dai_startup()
[all …]
H A Dlochnagar-sc.c20 struct clk *mclk; member
95 ret = clk_prepare_enable(priv->mclk); in lochnagar_sc_line_startup()
97 dev_err(dai->dev, "Failed to enable MCLK: %d\n", ret); in lochnagar_sc_line_startup()
116 clk_disable_unprepare(priv->mclk); in lochnagar_sc_line_shutdown()
232 priv->mclk = devm_clk_get(&pdev->dev, "mclk"); in lochnagar_sc_probe()
233 if (IS_ERR(priv->mclk)) { in lochnagar_sc_probe()
234 ret = PTR_ERR(priv->mclk); in lochnagar_sc_probe()
235 dev_err(&pdev->dev, "Failed to get MCLK: %d\n", ret); in lochnagar_sc_probe()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Drv730_dpm.c120 LPRV7XX_SMC_MCLK_VALUE mclk) in rv730_populate_mclk_value() argument
185 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_mclk_value()
186 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_mclk_value()
187 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
188 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_mclk_value()
189 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_mclk_value()
190 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_mclk_value()
191 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); in rv730_populate_mclk_value()
192 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv730_populate_mclk_value()
296 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
[all …]
H A Drv740_dpm.c115 DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n"); in rv740_get_dll_speed()
188 RV7XX_SMC_MCLK_VALUE *mclk) in rv740_populate_mclk_value() argument
271 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
272 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_mclk_value()
273 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_mclk_value()
274 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_mclk_value()
275 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_mclk_value()
276 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_mclk_value()
277 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv740_populate_mclk_value()
278 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); in rv740_populate_mclk_value()
[all …]
H A Drv770_dpm.c387 RV7XX_SMC_MCLK_VALUE *mclk) in rv770_populate_mclk_value() argument
472 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
473 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv770_populate_mclk_value()
474 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv770_populate_mclk_value()
475 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv770_populate_mclk_value()
476 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv770_populate_mclk_value()
477 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv770_populate_mclk_value()
478 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv770_populate_mclk_value()
591 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in rv770_populate_mvdd_value() argument
602 if (mclk <= pi->mvdd_split_frequency) { in rv770_populate_mvdd_value()
[all …]
H A Dcypress_dpm.c424 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in cypress_get_strobe_mode_settings() argument
431 if (mclk <= pi->mclk_strobe_mode_threshold) in cypress_get_strobe_mode_settings()
433 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode); in cypress_get_strobe_mode_settings()
476 RV7XX_SMC_MCLK_VALUE *mclk, in cypress_populate_mclk_value() argument
598 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
599 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in cypress_populate_mclk_value()
600 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in cypress_populate_mclk_value()
601 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in cypress_populate_mclk_value()
602 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in cypress_populate_mclk_value()
603 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in cypress_populate_mclk_value()
[all …]
H A Dbtc_dpm.c1244 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1248 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1255 (btc_blacklist_clocks[i].mclk == *mclk)) in btc_skip_blacklist_clocks()
1264 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1274 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1277 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1280 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1284 (pl->mclk + in btc_adjust_clock_combinations()
1288 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/mxs/
H A Dmxs-sgtl5000.c26 u32 mclk; in mxs_sgtl5000_hw_params() local
32 mclk = 256 * rate; in mxs_sgtl5000_hw_params()
35 mclk = 512 * rate; in mxs_sgtl5000_hw_params()
39 /* Set SGTL5000's SYSCLK (provided by SAIF MCLK) */ in mxs_sgtl5000_hw_params()
40 ret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, mclk, 0); in mxs_sgtl5000_hw_params()
43 mclk / 1000000, mclk / 1000 % 1000); in mxs_sgtl5000_hw_params()
47 /* The SAIF MCLK should be the same as SGTL5000_SYSCLK */ in mxs_sgtl5000_hw_params()
48 ret = snd_soc_dai_set_sysclk(cpu_dai, MXS_SAIF_MCLK, mclk, 0); in mxs_sgtl5000_hw_params()
51 mclk / 1000000, mclk / 1000 % 1000); in mxs_sgtl5000_hw_params()
142 * The Sgtl5000 sysclk is derived from saif0 mclk and it's range in mxs_sgtl5000_probe()
[all …]
H A Dmxs-saif.c55 saif->mclk = freq; in mxs_saif_set_dai_sysclk()
75 * Set SAIF clock and MCLK
78 unsigned int mclk, in mxs_saif_set_clk() argument
85 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); in mxs_saif_set_clk()
110 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. in mxs_saif_set_clk()
114 * If MCLK is not used, we just set saif clk to 512*fs. in mxs_saif_set_clk()
121 switch (mclk / rate) { in mxs_saif_set_clk()
138 /* SAIF MCLK should be a sub-rate of 512x or 384x */ in mxs_saif_set_clk()
160 * Program the over-sample rate for MCLK output in mxs_saif_set_clk()
162 * The available MCLK range is 32x, 48x... 512x. The rate in mxs_saif_set_clk()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/rockchip/
H A Drockchip_rt5651.c54 int mclk, ret; in rockchip_rt5651_hw_params() local
56 /* in bypass mode, the mclk has to be one of the frequencies below */ in rockchip_rt5651_hw_params()
65 mclk = 12288000; in rockchip_rt5651_hw_params()
71 mclk = 11289600; in rockchip_rt5651_hw_params()
77 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, SND_SOC_CLOCK_OUT); in rockchip_rt5651_hw_params()
83 snd_soc_dai_set_pll(codec_dai, 0, RT5651_PLL1_S_MCLK, mclk, mclk * 2); in rockchip_rt5651_hw_params()
85 ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1, mclk * 2, in rockchip_rt5651_hw_params()
100 int mclk, ret; in rockchip_rt5651_voice_hw_params() local
102 /* in bypass mode, the mclk has to be one of the frequencies below */ in rockchip_rt5651_voice_hw_params()
111 mclk = 12288000; in rockchip_rt5651_voice_hw_params()
[all …]
H A Drk3399_gru_sound.c68 unsigned int mclk; in rockchip_sound_max98357a_hw_params() local
71 mclk = params_rate(params) * SOUND_FS; in rockchip_sound_max98357a_hw_params()
73 ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), 0, mclk, 0); in rockchip_sound_max98357a_hw_params()
76 __func__, mclk, ret); in rockchip_sound_max98357a_hw_params()
89 unsigned int mclk; in rockchip_sound_rt5514_hw_params() local
92 mclk = params_rate(params) * SOUND_FS; in rockchip_sound_rt5514_hw_params()
94 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, in rockchip_sound_rt5514_hw_params()
102 mclk, SND_SOC_CLOCK_IN); in rockchip_sound_rt5514_hw_params()
121 int mclk, ret; in rockchip_sound_da7219_hw_params() local
123 /* in bypass mode, the mclk has to be one of the frequencies below */ in rockchip_sound_da7219_hw_params()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/intel/boards/
H A Dcht_bsw_rt5672.c26 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
33 struct clk *mclk; member
64 if (ctx->mclk) { in platform_clock_control()
65 ret = clk_prepare_enable(ctx->mclk); in platform_clock_control()
68 "could not configure MCLK state"); in platform_clock_control()
73 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ in platform_clock_control()
90 * PLL will be off when idle and MCLK will also be off by ACPI in platform_clock_control()
97 if (ctx->mclk) in platform_clock_control()
98 clk_disable_unprepare(ctx->mclk); in platform_clock_control()
150 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ in cht_aif1_hw_params()
[all …]
H A Dkbl_rt5663_rt5514_max98927.c56 struct clk *mclk; member
88 * MCLK/SCLK need to be ON early for a successful synchronization of in platform_clock_control()
94 /* Enable MCLK */ in platform_clock_control()
95 ret = clk_set_rate(priv->mclk, 24000000); in platform_clock_control()
97 dev_err(card->dev, "Can't set rate for mclk, err: %d\n", in platform_clock_control()
102 ret = clk_prepare_enable(priv->mclk); in platform_clock_control()
104 dev_err(card->dev, "Can't enable mclk, err: %d\n", ret); in platform_clock_control()
113 clk_disable_unprepare(priv->mclk); in platform_clock_control()
120 clk_disable_unprepare(priv->mclk); in platform_clock_control()
124 clk_disable_unprepare(priv->mclk); in platform_clock_control()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/ti/
H A Ddavinci-evm.c25 struct clk *mclk; member
36 if (drvdata->mclk) in evm_startup()
37 return clk_prepare_enable(drvdata->mclk); in evm_startup()
49 if (drvdata->mclk) in evm_shutdown()
50 clk_disable_unprepare(drvdata->mclk); in evm_shutdown()
390 struct clk *mclk; in davinci_evm_probe() local
418 mclk = devm_clk_get(&pdev->dev, "mclk"); in davinci_evm_probe()
419 if (PTR_ERR(mclk) == -EPROBE_DEFER) { in davinci_evm_probe()
421 } else if (IS_ERR(mclk)) { in davinci_evm_probe()
422 dev_dbg(&pdev->dev, "mclk not found.\n"); in davinci_evm_probe()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/meson/
H A Daxg-tdm-interface.c106 if (!iface->mclk) { in axg_tdm_iface_set_sysclk()
109 ret = clk_set_rate(iface->mclk, freq); in axg_tdm_iface_set_sysclk()
124 if (!iface->mclk) { in axg_tdm_iface_set_fmt()
125 dev_err(dai->dev, "cpu clock master: mclk missing\n"); in axg_tdm_iface_set_fmt()
269 /* If no specific mclk is requested, default to bit clock * 4 */ in axg_tdm_iface_set_sclk()
270 clk_set_rate(iface->mclk, 4 * srate); in axg_tdm_iface_set_sclk()
272 /* Check if we can actually get the bit clock from mclk */ in axg_tdm_iface_set_sclk()
275 "can't derive sclk %lu from mclk %lu\n", in axg_tdm_iface_set_sclk()
454 ret = clk_prepare_enable(iface->mclk); in axg_tdm_iface_set_bias_level()
459 clk_disable_unprepare(iface->mclk); in axg_tdm_iface_set_bias_level()
[all …]
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Drk1000-core.c36 struct clk *mclk; member
105 rk1000->mclk = devm_clk_get(rk1000->dev, "mclk"); in rk1000_probe()
106 if (IS_ERR(rk1000->mclk)) { in rk1000_probe()
107 dev_err(rk1000->dev, "get mclk err\n"); in rk1000_probe()
108 return PTR_ERR(rk1000->mclk); in rk1000_probe()
111 ret = clk_prepare_enable(rk1000->mclk); in rk1000_probe()
113 dev_err(rk1000->dev, "prepare mclk err\n"); in rk1000_probe()
137 clk_disable_unprepare(rk1000->mclk); in rk1000_probe()
145 clk_disable_unprepare(rk1000->mclk); in rk1000_remove()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-lochnagar.c50 LN_PARENT("ln-spdif-mclk"),
51 LN_PARENT("ln-psia1-mclk"),
52 LN_PARENT("ln-psia2-mclk"),
67 LN_PARENT("ln-spdif-mclk"),
77 LN_PARENT("ln-psia1-mclk"),
78 LN_PARENT("ln-psia2-mclk"),
80 LN_PARENT("ln-adat-mclk"),
115 LN2_CLK(PSIA1_MCLK, "ln-psia1-mclk"),
116 LN2_CLK(PSIA2_MCLK, "ln-psia2-mclk"),
117 LN2_CLK(SPDIF_MCLK, "ln-spdif-mclk"),
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dstv0900_sw.c42 max_carrier /= intp->mclk / 1000; in stv0900_check_signal_presence()
69 max_carrier /= intp->mclk / 1000; in stv0900_get_sw_loop_params()
75 freq_inc /= intp->mclk >> 10; in stv0900_get_sw_loop_params()
135 max_carrier /= intp->mclk / 1000; in stv0900_search_carr_sw_loop()
295 u32 mclk, in stv0900_get_symbol_rate() argument
310 intval1 = (mclk) >> 16; in stv0900_get_symbol_rate()
313 rem1 = (mclk) % 0x10000; in stv0900_get_symbol_rate()
323 u32 mclk, u32 srate, in stv0900_set_symbol_rate() argument
328 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk, in stv0900_set_symbol_rate()
333 symb /= (mclk >> 12); in stv0900_set_symbol_rate()
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi164 clock-names = "ipg", "ips", "sys", "ref", "mclk";
176 clock-names = "ipg", "ips", "sys", "ref", "mclk";
250 clock-names = "ipg", "ips", "sys", "ref", "mclk";
262 clock-names = "ipg", "ips", "sys", "ref", "mclk";
357 clock-names = "ipg", "mclk";
369 clock-names = "ipg", "mclk";
381 clock-names = "ipg", "mclk";
393 clock-names = "ipg", "mclk";
405 clock-names = "ipg", "mclk";
417 clock-names = "ipg", "mclk";
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dmt8173-rt5650.txt16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
26 mediatek,mclk = <0>;
/OK3568_Linux_fs/kernel/sound/soc/intel/skylake/
H A Dskl-i2s.h26 #define get_clk_src(mclk, mask) \ argument
27 ((mclk.mdivctrl & mask) >> SKL_SHIFT(mask))
71 * @mclk: MCLK clock source and divider values
77 struct skl_i2s_config_mclk mclk; member
85 struct skl_i2s_config_mclk_ext mclk; member

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