1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * skl-i2s.h - i2s blob mapping 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Intel Corp 6*4882a593Smuzhiyun * Author: Subhransu S. Prusty < subhransu.s.prusty@intel.com> 7*4882a593Smuzhiyun * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __SOUND_SOC_SKL_I2S_H 13*4882a593Smuzhiyun #define __SOUND_SOC_SKL_I2S_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SKL_I2S_MAX_TIME_SLOTS 8 16*4882a593Smuzhiyun #define SKL_MCLK_DIV_CLK_SRC_MASK GENMASK(17, 16) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define SKL_MNDSS_DIV_CLK_SRC_MASK GENMASK(21, 20) 19*4882a593Smuzhiyun #define SKL_SHIFT(x) (ffs(x) - 1) 20*4882a593Smuzhiyun #define SKL_MCLK_DIV_RATIO_MASK GENMASK(11, 0) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define is_legacy_blob(x) (x.signature != 0xEE) 23*4882a593Smuzhiyun #define ext_to_legacy_blob(i2s_config_blob_ext) \ 24*4882a593Smuzhiyun ((struct skl_i2s_config_blob_legacy *) i2s_config_blob_ext) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define get_clk_src(mclk, mask) \ 27*4882a593Smuzhiyun ((mclk.mdivctrl & mask) >> SKL_SHIFT(mask)) 28*4882a593Smuzhiyun struct skl_i2s_config { 29*4882a593Smuzhiyun u32 ssc0; 30*4882a593Smuzhiyun u32 ssc1; 31*4882a593Smuzhiyun u32 sscto; 32*4882a593Smuzhiyun u32 sspsp; 33*4882a593Smuzhiyun u32 sstsa; 34*4882a593Smuzhiyun u32 ssrsa; 35*4882a593Smuzhiyun u32 ssc2; 36*4882a593Smuzhiyun u32 sspsp2; 37*4882a593Smuzhiyun u32 ssc3; 38*4882a593Smuzhiyun u32 ssioc; 39*4882a593Smuzhiyun } __packed; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct skl_i2s_config_mclk { 42*4882a593Smuzhiyun u32 mdivctrl; 43*4882a593Smuzhiyun u32 mdivr; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct skl_i2s_config_mclk_ext { 47*4882a593Smuzhiyun u32 mdivctrl; 48*4882a593Smuzhiyun u32 mdivr_count; 49*4882a593Smuzhiyun u32 mdivr[]; 50*4882a593Smuzhiyun } __packed; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct skl_i2s_config_blob_signature { 53*4882a593Smuzhiyun u32 minor_ver : 8; 54*4882a593Smuzhiyun u32 major_ver : 8; 55*4882a593Smuzhiyun u32 resvdz : 8; 56*4882a593Smuzhiyun u32 signature : 8; 57*4882a593Smuzhiyun } __packed; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct skl_i2s_config_blob_header { 60*4882a593Smuzhiyun struct skl_i2s_config_blob_signature sig; 61*4882a593Smuzhiyun u32 size; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /** 65*4882a593Smuzhiyun * struct skl_i2s_config_blob_legacy - Structure defines I2S Gateway 66*4882a593Smuzhiyun * configuration legacy blob 67*4882a593Smuzhiyun * 68*4882a593Smuzhiyun * @gtw_attr: Gateway attribute for the I2S Gateway 69*4882a593Smuzhiyun * @tdm_ts_group: TDM slot mapping against channels in the Gateway. 70*4882a593Smuzhiyun * @i2s_cfg: I2S HW registers 71*4882a593Smuzhiyun * @mclk: MCLK clock source and divider values 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun struct skl_i2s_config_blob_legacy { 74*4882a593Smuzhiyun u32 gtw_attr; 75*4882a593Smuzhiyun u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS]; 76*4882a593Smuzhiyun struct skl_i2s_config i2s_cfg; 77*4882a593Smuzhiyun struct skl_i2s_config_mclk mclk; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct skl_i2s_config_blob_ext { 81*4882a593Smuzhiyun u32 gtw_attr; 82*4882a593Smuzhiyun struct skl_i2s_config_blob_header hdr; 83*4882a593Smuzhiyun u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS]; 84*4882a593Smuzhiyun struct skl_i2s_config i2s_cfg; 85*4882a593Smuzhiyun struct skl_i2s_config_mclk_ext mclk; 86*4882a593Smuzhiyun } __packed; 87*4882a593Smuzhiyun #endif /* __SOUND_SOC_SKL_I2S_H */ 88