1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2018 BayLibre, SAS.
4*4882a593Smuzhiyun // Author: Jerome Brunet <jbrunet@baylibre.com>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/of_platform.h>
9*4882a593Smuzhiyun #include <sound/pcm_params.h>
10*4882a593Smuzhiyun #include <sound/soc.h>
11*4882a593Smuzhiyun #include <sound/soc-dai.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "axg-tdm.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun enum {
16*4882a593Smuzhiyun TDM_IFACE_PAD,
17*4882a593Smuzhiyun TDM_IFACE_LOOPBACK,
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
axg_tdm_slots_total(u32 * mask)20*4882a593Smuzhiyun static unsigned int axg_tdm_slots_total(u32 *mask)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun unsigned int slots = 0;
23*4882a593Smuzhiyun int i;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun if (!mask)
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Count the total number of slots provided by all 4 lanes */
29*4882a593Smuzhiyun for (i = 0; i < AXG_TDM_NUM_LANES; i++)
30*4882a593Smuzhiyun slots += hweight32(mask[i]);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun return slots;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
axg_tdm_set_tdm_slots(struct snd_soc_dai * dai,u32 * tx_mask,u32 * rx_mask,unsigned int slots,unsigned int slot_width)35*4882a593Smuzhiyun int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
36*4882a593Smuzhiyun u32 *rx_mask, unsigned int slots,
37*4882a593Smuzhiyun unsigned int slot_width)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
40*4882a593Smuzhiyun struct axg_tdm_stream *tx = (struct axg_tdm_stream *)
41*4882a593Smuzhiyun dai->playback_dma_data;
42*4882a593Smuzhiyun struct axg_tdm_stream *rx = (struct axg_tdm_stream *)
43*4882a593Smuzhiyun dai->capture_dma_data;
44*4882a593Smuzhiyun unsigned int tx_slots, rx_slots;
45*4882a593Smuzhiyun unsigned int fmt = 0;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun tx_slots = axg_tdm_slots_total(tx_mask);
48*4882a593Smuzhiyun rx_slots = axg_tdm_slots_total(rx_mask);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* We should at least have a slot for a valid interface */
51*4882a593Smuzhiyun if (!tx_slots && !rx_slots) {
52*4882a593Smuzhiyun dev_err(dai->dev, "interface has no slot\n");
53*4882a593Smuzhiyun return -EINVAL;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun iface->slots = slots;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun switch (slot_width) {
59*4882a593Smuzhiyun case 0:
60*4882a593Smuzhiyun slot_width = 32;
61*4882a593Smuzhiyun fallthrough;
62*4882a593Smuzhiyun case 32:
63*4882a593Smuzhiyun fmt |= SNDRV_PCM_FMTBIT_S32_LE;
64*4882a593Smuzhiyun fallthrough;
65*4882a593Smuzhiyun case 24:
66*4882a593Smuzhiyun fmt |= SNDRV_PCM_FMTBIT_S24_LE;
67*4882a593Smuzhiyun fmt |= SNDRV_PCM_FMTBIT_S20_LE;
68*4882a593Smuzhiyun fallthrough;
69*4882a593Smuzhiyun case 16:
70*4882a593Smuzhiyun fmt |= SNDRV_PCM_FMTBIT_S16_LE;
71*4882a593Smuzhiyun fallthrough;
72*4882a593Smuzhiyun case 8:
73*4882a593Smuzhiyun fmt |= SNDRV_PCM_FMTBIT_S8;
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun default:
76*4882a593Smuzhiyun dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
77*4882a593Smuzhiyun return -EINVAL;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun iface->slot_width = slot_width;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Amend the dai driver and let dpcm merge do its job */
83*4882a593Smuzhiyun if (tx) {
84*4882a593Smuzhiyun tx->mask = tx_mask;
85*4882a593Smuzhiyun dai->driver->playback.channels_max = tx_slots;
86*4882a593Smuzhiyun dai->driver->playback.formats = fmt;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (rx) {
90*4882a593Smuzhiyun rx->mask = rx_mask;
91*4882a593Smuzhiyun dai->driver->capture.channels_max = rx_slots;
92*4882a593Smuzhiyun dai->driver->capture.formats = fmt;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
98*4882a593Smuzhiyun
axg_tdm_iface_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)99*4882a593Smuzhiyun static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
100*4882a593Smuzhiyun unsigned int freq, int dir)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
103*4882a593Smuzhiyun int ret = -ENOTSUPP;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
106*4882a593Smuzhiyun if (!iface->mclk) {
107*4882a593Smuzhiyun dev_warn(dai->dev, "master clock not provided\n");
108*4882a593Smuzhiyun } else {
109*4882a593Smuzhiyun ret = clk_set_rate(iface->mclk, freq);
110*4882a593Smuzhiyun if (!ret)
111*4882a593Smuzhiyun iface->mclk_rate = freq;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return ret;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
axg_tdm_iface_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)118*4882a593Smuzhiyun static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
123*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
124*4882a593Smuzhiyun if (!iface->mclk) {
125*4882a593Smuzhiyun dev_err(dai->dev, "cpu clock master: mclk missing\n");
126*4882a593Smuzhiyun return -ENODEV;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
131*4882a593Smuzhiyun break;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFM:
134*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFS:
135*4882a593Smuzhiyun dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
136*4882a593Smuzhiyun fallthrough;
137*4882a593Smuzhiyun default:
138*4882a593Smuzhiyun return -EINVAL;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun iface->fmt = fmt;
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
axg_tdm_iface_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)145*4882a593Smuzhiyun static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
146*4882a593Smuzhiyun struct snd_soc_dai *dai)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
149*4882a593Smuzhiyun struct axg_tdm_stream *ts =
150*4882a593Smuzhiyun snd_soc_dai_get_dma_data(dai, substream);
151*4882a593Smuzhiyun int ret;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (!axg_tdm_slots_total(ts->mask)) {
154*4882a593Smuzhiyun dev_err(dai->dev, "interface has not slots\n");
155*4882a593Smuzhiyun return -EINVAL;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* Apply component wide rate symmetry */
159*4882a593Smuzhiyun if (snd_soc_component_active(dai->component)) {
160*4882a593Smuzhiyun ret = snd_pcm_hw_constraint_single(substream->runtime,
161*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE,
162*4882a593Smuzhiyun iface->rate);
163*4882a593Smuzhiyun if (ret < 0) {
164*4882a593Smuzhiyun dev_err(dai->dev,
165*4882a593Smuzhiyun "can't set iface rate constraint\n");
166*4882a593Smuzhiyun return ret;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
axg_tdm_iface_set_stream(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)173*4882a593Smuzhiyun static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
174*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
175*4882a593Smuzhiyun struct snd_soc_dai *dai)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
178*4882a593Smuzhiyun struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
179*4882a593Smuzhiyun unsigned int channels = params_channels(params);
180*4882a593Smuzhiyun unsigned int width = params_width(params);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* Save rate and sample_bits for component symmetry */
183*4882a593Smuzhiyun iface->rate = params_rate(params);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* Make sure this interface can cope with the stream */
186*4882a593Smuzhiyun if (axg_tdm_slots_total(ts->mask) < channels) {
187*4882a593Smuzhiyun dev_err(dai->dev, "not enough slots for channels\n");
188*4882a593Smuzhiyun return -EINVAL;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun if (iface->slot_width < width) {
192*4882a593Smuzhiyun dev_err(dai->dev, "incompatible slots width for stream\n");
193*4882a593Smuzhiyun return -EINVAL;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /* Save the parameter for tdmout/tdmin widgets */
197*4882a593Smuzhiyun ts->physical_width = params_physical_width(params);
198*4882a593Smuzhiyun ts->width = params_width(params);
199*4882a593Smuzhiyun ts->channels = params_channels(params);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun return 0;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
axg_tdm_iface_set_lrclk(struct snd_soc_dai * dai,struct snd_pcm_hw_params * params)204*4882a593Smuzhiyun static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
205*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
208*4882a593Smuzhiyun unsigned int ratio_num;
209*4882a593Smuzhiyun int ret;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun ret = clk_set_rate(iface->lrclk, params_rate(params));
212*4882a593Smuzhiyun if (ret) {
213*4882a593Smuzhiyun dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
214*4882a593Smuzhiyun return ret;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
218*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
219*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
220*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
221*4882a593Smuzhiyun /* 50% duty cycle ratio */
222*4882a593Smuzhiyun ratio_num = 1;
223*4882a593Smuzhiyun break;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
226*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
227*4882a593Smuzhiyun /*
228*4882a593Smuzhiyun * A zero duty cycle ratio will result in setting the mininum
229*4882a593Smuzhiyun * ratio possible which, for this clock, is 1 cycle of the
230*4882a593Smuzhiyun * parent bclk clock high and the rest low, This is exactly
231*4882a593Smuzhiyun * what we want here.
232*4882a593Smuzhiyun */
233*4882a593Smuzhiyun ratio_num = 0;
234*4882a593Smuzhiyun break;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun default:
237*4882a593Smuzhiyun return -EINVAL;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
241*4882a593Smuzhiyun if (ret) {
242*4882a593Smuzhiyun dev_err(dai->dev,
243*4882a593Smuzhiyun "setting sample clock duty cycle failed: %d\n", ret);
244*4882a593Smuzhiyun return ret;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /* Set sample clock inversion */
248*4882a593Smuzhiyun ret = clk_set_phase(iface->lrclk,
249*4882a593Smuzhiyun axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
250*4882a593Smuzhiyun if (ret) {
251*4882a593Smuzhiyun dev_err(dai->dev,
252*4882a593Smuzhiyun "setting sample clock phase failed: %d\n", ret);
253*4882a593Smuzhiyun return ret;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun return 0;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
axg_tdm_iface_set_sclk(struct snd_soc_dai * dai,struct snd_pcm_hw_params * params)259*4882a593Smuzhiyun static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
260*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
263*4882a593Smuzhiyun unsigned long srate;
264*4882a593Smuzhiyun int ret;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun srate = iface->slots * iface->slot_width * params_rate(params);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun if (!iface->mclk_rate) {
269*4882a593Smuzhiyun /* If no specific mclk is requested, default to bit clock * 4 */
270*4882a593Smuzhiyun clk_set_rate(iface->mclk, 4 * srate);
271*4882a593Smuzhiyun } else {
272*4882a593Smuzhiyun /* Check if we can actually get the bit clock from mclk */
273*4882a593Smuzhiyun if (iface->mclk_rate % srate) {
274*4882a593Smuzhiyun dev_err(dai->dev,
275*4882a593Smuzhiyun "can't derive sclk %lu from mclk %lu\n",
276*4882a593Smuzhiyun srate, iface->mclk_rate);
277*4882a593Smuzhiyun return -EINVAL;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun ret = clk_set_rate(iface->sclk, srate);
282*4882a593Smuzhiyun if (ret) {
283*4882a593Smuzhiyun dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
284*4882a593Smuzhiyun return ret;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /* Set the bit clock inversion */
288*4882a593Smuzhiyun ret = clk_set_phase(iface->sclk,
289*4882a593Smuzhiyun axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
290*4882a593Smuzhiyun if (ret) {
291*4882a593Smuzhiyun dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
292*4882a593Smuzhiyun return ret;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun return ret;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
axg_tdm_iface_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)298*4882a593Smuzhiyun static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
299*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
300*4882a593Smuzhiyun struct snd_soc_dai *dai)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
303*4882a593Smuzhiyun int ret;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
306*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
307*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
308*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
309*4882a593Smuzhiyun if (iface->slots > 2) {
310*4882a593Smuzhiyun dev_err(dai->dev, "bad slot number for format: %d\n",
311*4882a593Smuzhiyun iface->slots);
312*4882a593Smuzhiyun return -EINVAL;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun break;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
317*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
318*4882a593Smuzhiyun break;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun default:
321*4882a593Smuzhiyun dev_err(dai->dev, "unsupported dai format\n");
322*4882a593Smuzhiyun return -EINVAL;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun ret = axg_tdm_iface_set_stream(substream, params, dai);
326*4882a593Smuzhiyun if (ret)
327*4882a593Smuzhiyun return ret;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if ((iface->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
330*4882a593Smuzhiyun SND_SOC_DAIFMT_CBS_CFS) {
331*4882a593Smuzhiyun ret = axg_tdm_iface_set_sclk(dai, params);
332*4882a593Smuzhiyun if (ret)
333*4882a593Smuzhiyun return ret;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun ret = axg_tdm_iface_set_lrclk(dai, params);
336*4882a593Smuzhiyun if (ret)
337*4882a593Smuzhiyun return ret;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun return 0;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
axg_tdm_iface_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)343*4882a593Smuzhiyun static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
344*4882a593Smuzhiyun struct snd_soc_dai *dai)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /* Stop all attached formatters */
349*4882a593Smuzhiyun axg_tdm_stream_stop(ts);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return 0;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
axg_tdm_iface_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)354*4882a593Smuzhiyun static int axg_tdm_iface_prepare(struct snd_pcm_substream *substream,
355*4882a593Smuzhiyun struct snd_soc_dai *dai)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun /* Force all attached formatters to update */
360*4882a593Smuzhiyun return axg_tdm_stream_reset(ts);
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
axg_tdm_iface_remove_dai(struct snd_soc_dai * dai)363*4882a593Smuzhiyun static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun if (dai->capture_dma_data)
366*4882a593Smuzhiyun axg_tdm_stream_free(dai->capture_dma_data);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun if (dai->playback_dma_data)
369*4882a593Smuzhiyun axg_tdm_stream_free(dai->playback_dma_data);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun return 0;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
axg_tdm_iface_probe_dai(struct snd_soc_dai * dai)374*4882a593Smuzhiyun static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun if (dai->capture_widget) {
379*4882a593Smuzhiyun dai->capture_dma_data = axg_tdm_stream_alloc(iface);
380*4882a593Smuzhiyun if (!dai->capture_dma_data)
381*4882a593Smuzhiyun return -ENOMEM;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun if (dai->playback_widget) {
385*4882a593Smuzhiyun dai->playback_dma_data = axg_tdm_stream_alloc(iface);
386*4882a593Smuzhiyun if (!dai->playback_dma_data) {
387*4882a593Smuzhiyun axg_tdm_iface_remove_dai(dai);
388*4882a593Smuzhiyun return -ENOMEM;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun return 0;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
396*4882a593Smuzhiyun .set_sysclk = axg_tdm_iface_set_sysclk,
397*4882a593Smuzhiyun .set_fmt = axg_tdm_iface_set_fmt,
398*4882a593Smuzhiyun .startup = axg_tdm_iface_startup,
399*4882a593Smuzhiyun .hw_params = axg_tdm_iface_hw_params,
400*4882a593Smuzhiyun .prepare = axg_tdm_iface_prepare,
401*4882a593Smuzhiyun .hw_free = axg_tdm_iface_hw_free,
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun /* TDM Backend DAIs */
405*4882a593Smuzhiyun static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
406*4882a593Smuzhiyun [TDM_IFACE_PAD] = {
407*4882a593Smuzhiyun .name = "TDM Pad",
408*4882a593Smuzhiyun .playback = {
409*4882a593Smuzhiyun .stream_name = "Playback",
410*4882a593Smuzhiyun .channels_min = 1,
411*4882a593Smuzhiyun .channels_max = AXG_TDM_CHANNEL_MAX,
412*4882a593Smuzhiyun .rates = AXG_TDM_RATES,
413*4882a593Smuzhiyun .formats = AXG_TDM_FORMATS,
414*4882a593Smuzhiyun },
415*4882a593Smuzhiyun .capture = {
416*4882a593Smuzhiyun .stream_name = "Capture",
417*4882a593Smuzhiyun .channels_min = 1,
418*4882a593Smuzhiyun .channels_max = AXG_TDM_CHANNEL_MAX,
419*4882a593Smuzhiyun .rates = AXG_TDM_RATES,
420*4882a593Smuzhiyun .formats = AXG_TDM_FORMATS,
421*4882a593Smuzhiyun },
422*4882a593Smuzhiyun .id = TDM_IFACE_PAD,
423*4882a593Smuzhiyun .ops = &axg_tdm_iface_ops,
424*4882a593Smuzhiyun .probe = axg_tdm_iface_probe_dai,
425*4882a593Smuzhiyun .remove = axg_tdm_iface_remove_dai,
426*4882a593Smuzhiyun },
427*4882a593Smuzhiyun [TDM_IFACE_LOOPBACK] = {
428*4882a593Smuzhiyun .name = "TDM Loopback",
429*4882a593Smuzhiyun .capture = {
430*4882a593Smuzhiyun .stream_name = "Loopback",
431*4882a593Smuzhiyun .channels_min = 1,
432*4882a593Smuzhiyun .channels_max = AXG_TDM_CHANNEL_MAX,
433*4882a593Smuzhiyun .rates = AXG_TDM_RATES,
434*4882a593Smuzhiyun .formats = AXG_TDM_FORMATS,
435*4882a593Smuzhiyun },
436*4882a593Smuzhiyun .id = TDM_IFACE_LOOPBACK,
437*4882a593Smuzhiyun .ops = &axg_tdm_iface_ops,
438*4882a593Smuzhiyun .probe = axg_tdm_iface_probe_dai,
439*4882a593Smuzhiyun .remove = axg_tdm_iface_remove_dai,
440*4882a593Smuzhiyun },
441*4882a593Smuzhiyun };
442*4882a593Smuzhiyun
axg_tdm_iface_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)443*4882a593Smuzhiyun static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
444*4882a593Smuzhiyun enum snd_soc_bias_level level)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
447*4882a593Smuzhiyun enum snd_soc_bias_level now =
448*4882a593Smuzhiyun snd_soc_component_get_bias_level(component);
449*4882a593Smuzhiyun int ret = 0;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun switch (level) {
452*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
453*4882a593Smuzhiyun if (now == SND_SOC_BIAS_STANDBY)
454*4882a593Smuzhiyun ret = clk_prepare_enable(iface->mclk);
455*4882a593Smuzhiyun break;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
458*4882a593Smuzhiyun if (now == SND_SOC_BIAS_PREPARE)
459*4882a593Smuzhiyun clk_disable_unprepare(iface->mclk);
460*4882a593Smuzhiyun break;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
463*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
464*4882a593Smuzhiyun break;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun return ret;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun static const struct snd_soc_dapm_widget axg_tdm_iface_dapm_widgets[] = {
471*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("Playback Signal"),
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun static const struct snd_soc_dapm_route axg_tdm_iface_dapm_routes[] = {
475*4882a593Smuzhiyun { "Loopback", NULL, "Playback Signal" },
476*4882a593Smuzhiyun };
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
479*4882a593Smuzhiyun .dapm_widgets = axg_tdm_iface_dapm_widgets,
480*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(axg_tdm_iface_dapm_widgets),
481*4882a593Smuzhiyun .dapm_routes = axg_tdm_iface_dapm_routes,
482*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(axg_tdm_iface_dapm_routes),
483*4882a593Smuzhiyun .set_bias_level = axg_tdm_iface_set_bias_level,
484*4882a593Smuzhiyun };
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun static const struct of_device_id axg_tdm_iface_of_match[] = {
487*4882a593Smuzhiyun { .compatible = "amlogic,axg-tdm-iface", },
488*4882a593Smuzhiyun {}
489*4882a593Smuzhiyun };
490*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
491*4882a593Smuzhiyun
axg_tdm_iface_probe(struct platform_device * pdev)492*4882a593Smuzhiyun static int axg_tdm_iface_probe(struct platform_device *pdev)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun struct device *dev = &pdev->dev;
495*4882a593Smuzhiyun struct snd_soc_dai_driver *dai_drv;
496*4882a593Smuzhiyun struct axg_tdm_iface *iface;
497*4882a593Smuzhiyun int ret, i;
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
500*4882a593Smuzhiyun if (!iface)
501*4882a593Smuzhiyun return -ENOMEM;
502*4882a593Smuzhiyun platform_set_drvdata(pdev, iface);
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /*
505*4882a593Smuzhiyun * Duplicate dai driver: depending on the slot masks configuration
506*4882a593Smuzhiyun * We'll change the number of channel provided by DAI stream, so dpcm
507*4882a593Smuzhiyun * channel merge can be done properly
508*4882a593Smuzhiyun */
509*4882a593Smuzhiyun dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
510*4882a593Smuzhiyun sizeof(*dai_drv), GFP_KERNEL);
511*4882a593Smuzhiyun if (!dai_drv)
512*4882a593Smuzhiyun return -ENOMEM;
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
515*4882a593Smuzhiyun memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
516*4882a593Smuzhiyun sizeof(*dai_drv));
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun /* Bit clock provided on the pad */
519*4882a593Smuzhiyun iface->sclk = devm_clk_get(dev, "sclk");
520*4882a593Smuzhiyun if (IS_ERR(iface->sclk)) {
521*4882a593Smuzhiyun ret = PTR_ERR(iface->sclk);
522*4882a593Smuzhiyun if (ret != -EPROBE_DEFER)
523*4882a593Smuzhiyun dev_err(dev, "failed to get sclk: %d\n", ret);
524*4882a593Smuzhiyun return ret;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun /* Sample clock provided on the pad */
528*4882a593Smuzhiyun iface->lrclk = devm_clk_get(dev, "lrclk");
529*4882a593Smuzhiyun if (IS_ERR(iface->lrclk)) {
530*4882a593Smuzhiyun ret = PTR_ERR(iface->lrclk);
531*4882a593Smuzhiyun if (ret != -EPROBE_DEFER)
532*4882a593Smuzhiyun dev_err(dev, "failed to get lrclk: %d\n", ret);
533*4882a593Smuzhiyun return ret;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun /*
537*4882a593Smuzhiyun * mclk maybe be missing when the cpu dai is in slave mode and
538*4882a593Smuzhiyun * the codec does not require it to provide a master clock.
539*4882a593Smuzhiyun * At this point, ignore the error if mclk is missing. We'll
540*4882a593Smuzhiyun * throw an error if the cpu dai is master and mclk is missing
541*4882a593Smuzhiyun */
542*4882a593Smuzhiyun iface->mclk = devm_clk_get(dev, "mclk");
543*4882a593Smuzhiyun if (IS_ERR(iface->mclk)) {
544*4882a593Smuzhiyun ret = PTR_ERR(iface->mclk);
545*4882a593Smuzhiyun if (ret == -ENOENT) {
546*4882a593Smuzhiyun iface->mclk = NULL;
547*4882a593Smuzhiyun } else {
548*4882a593Smuzhiyun if (ret != -EPROBE_DEFER)
549*4882a593Smuzhiyun dev_err(dev, "failed to get mclk: %d\n", ret);
550*4882a593Smuzhiyun return ret;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun return devm_snd_soc_register_component(dev,
555*4882a593Smuzhiyun &axg_tdm_iface_component_drv, dai_drv,
556*4882a593Smuzhiyun ARRAY_SIZE(axg_tdm_iface_dai_drv));
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun static struct platform_driver axg_tdm_iface_pdrv = {
560*4882a593Smuzhiyun .probe = axg_tdm_iface_probe,
561*4882a593Smuzhiyun .driver = {
562*4882a593Smuzhiyun .name = "axg-tdm-iface",
563*4882a593Smuzhiyun .of_match_table = axg_tdm_iface_of_match,
564*4882a593Smuzhiyun },
565*4882a593Smuzhiyun };
566*4882a593Smuzhiyun module_platform_driver(axg_tdm_iface_pdrv);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
569*4882a593Smuzhiyun MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
570*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
571