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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.txt38 - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
39 - hs400-ds-delay: HS400 DS delay setting
43 - mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
46 - mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
47 If present,HS400 command responses are sampled on rising edges.
48 If not present,HS400 command responses are sampled on falling edges.
71 hs400-ds-delay = <0x14015>;
73 mediatek,hs400-cmd-int-delay = <14>;
74 mediatek,hs400-cmd-resp-sel-rising;
H A Dnvidia,tegra20-sdhci.txt79 - nvidia,pad-autocal-pull-up-offset-hs400,
80 nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
81 calibration offsets for HS400 mode.
86 - nvidia,dqs-trim : Specify DQS trim value for HS400 timing
94 - The SDR104 and HS400 timing specific values are used in
104 HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
105 HS400.
H A Dexynos-dw-mshc.txt39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
40 shift value for hs400 mode operation.
55 * samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
89 samsung,dw-mshc-hs400-timing = <0 2>;
H A Dcdns,sdhci.yaml93 HS200, HS400 and HS400_ES.
100 Value of the delay introduced on the sdclk output for HS200, HS400 and
109 HS400 / HS400_ES speed modes.
132 mmc-hs400-1_8v;
H A Dsdhci-sprd.txt40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
H A Dmmc-controller.yaml206 mmc-hs400-1_2v:
209 eMMC HS400 mode (1.2V I/O) is supported.
211 mmc-hs400-1_8v:
214 eMMC HS400 mode (1.8V I/O) is supported.
216 mmc-hs400-enhanced-strobe:
219 eMMC HS400 enhanced strobe mode is supported
H A Dsdhci-am654.yaml111 ti,otap-del-sel-hs400:
112 description: Output tap delay for eMMC HS400 timing
174 description: strobe select delay for HS400 speed mode.
213 ti,otap-del-sel-hs400 = <0x0>;
H A Dbrcm,sdhci-brcmstb.txt39 mmc-hs400-1_8v;
40 mmc-hs400-enhanced-strobe;
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-acpi.c569 * The initialization sequence for HS400 is:
570 * HS->HS200->Perform Tuning->HS->HS400
573 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
575 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
578 * HS400, we can re-enable the tuned clock.
603 /* DLL is only required for HS400 */ in amd_set_ios()
673 * b) The HS200 and HS400 driver strengths don't match. in sdhci_acpi_emmc_amd_probe_slot()
675 * A, but the (internal) HS400 preset register has a driver in sdhci_acpi_emmc_amd_probe_slot()
676 * strength of B. As part of initializing HS400, HS200 tuning in sdhci_acpi_emmc_amd_probe_slot()
683 * HS400 preset driver strengths match. in sdhci_acpi_emmc_amd_probe_slot()
[all …]
H A Drenesas_sdhi.h17 u32 tap; /* sampling clock position for SDR104/HS400 (8 TAP) */
18 u32 tap_hs400_4tap; /* sampling clock position for HS400 (4 TAP) */
H A Dsdhci-xenon-phy.c318 * and before HS400 data strobe setting.
436 /* Set HS400 Data Strobe and Enhanced Strobe */
449 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n"); in xenon_emmc_phy_strobe_delay_adj()
459 * 1. card is in HS400 mode and in xenon_emmc_phy_strobe_delay_adj()
638 /* Hardware team recommend a value for HS400 */ in xenon_emmc_phy_set()
732 * HS400 set Data Strobe and Enhanced Strobe if it is supported.
H A Ddw_mmc-exynos.c239 * related to HS400 in dw_mci_exynos_config_hs400()
244 "cannot configure HS400, unsupported chipset\n"); in dw_mci_exynos_config_hs400()
331 /* Configure setting for HS400 */ in dw_mci_exynos_set_ios()
380 "samsung,dw-mshc-hs400-timing", timing, 2); in dw_mci_exynos_parse_dt()
H A Dsdhci-xenon.c192 * Xenon defines different values for HS200 and HS400
273 * HS400/HS200/eMMC HS doesn't have Preset Value register. in xenon_set_ios()
274 * However, sdhci_set_ios will read HS400/HS200 Preset register. in xenon_set_ios()
275 * Disable Preset Value register for HS400/HS200. in xenon_set_ios()
H A Dsdhci-of-esdhc.c682 /* Limit clock division for HS400 200MHz clock for quirk. */ in esdhc_of_set_clock()
738 /* Additional setting for HS400. */ in esdhc_of_set_clock()
1125 /* Recover HS400 tuning flag */ in esdhc_execute_tuning()
1142 /* Recover HS400 tuning flag */ in esdhc_execute_tuning()
1175 * There are specific registers setting for HS400 mode. in esdhc_set_uhs_signaling()
1176 * Clean all of them if controller is in HS400 mode to in esdhc_set_uhs_signaling()
1177 * exit HS400 mode before re-setting any speed mode. in esdhc_set_uhs_signaling()
H A Dsdhci-msm.c469 * HS400/HS200 timing mode).
819 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC in msm_hc_select_hs400()
858 * eMMC specific HS200/HS400 doesn't have their respective modes
862 * HS400 - This involves multiple configurations
864 * Then when switching to DDR @ 400MHz (HS400) we use
870 * HS400 - divided clock (free running MCLK/2)
896 * Retuning in HS400 (DDR mode) will fail, just reset the in sdhci_msm_cdclp533_calibration()
1076 * Retuning in HS400 (DDR mode) will fail, just reset the in sdhci_msm_hs400_dll_calibration()
1111 * Tuning is required for SDR104, HS200 and HS400 cards and in sdhci_msm_is_tuning_needed()
1190 * HS400 settings. in sdhci_msm_execute_tuning()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-nanopc-t4.dts112 mmc-hs400-1_8v;
113 mmc-hs400-enhanced-strobe;
/OK3568_Linux_fs/kernel/include/linux/mmc/
H A Dhost.h152 /* Prepare HS400 target operating frequency depending host driver */
155 /* Prepare switch to DDR during the HS400 init sequence */
158 /* Prepare for switching from HS400 to HS200 */
161 /* Complete selection of HS400 */
372 #define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */
373 #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi146 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
156 mmc-hs400-enhanced-strobe;
157 mmc-hs400-1_8v;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3528-u-boot.dtsi105 mmc-hs400-1_8v;
106 mmc-hs400-enhanced-strobe;
H A Drk3562-u-boot.dtsi101 mmc-hs400-1_8v;
102 mmc-hs400-enhanced-strobe;
H A Drk3588-u-boot.dtsi176 mmc-hs400-1_8v;
177 mmc-hs400-enhanced-strobe;
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Drockchip_sdhci.c180 /* REN Enable on STRB Line for HS400 */ in rk3399_emmc_phy_power_on()
467 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ in dwcmshc_sdhci_set_ios_post()
572 else if (dev_read_bool(dev, "mmc-hs400-1_8v")) in rockchip_sdhci_probe()
575 if (data->set_enhanced_strobe && dev_read_bool(dev, "mmc-hs400-enhanced-strobe")) in rockchip_sdhci_probe()
/OK3568_Linux_fs/kernel/drivers/mmc/core/
H A Ddebugfs.c151 "mmc HS400 enhanced strobe" : "mmc HS400"; in mmc_ios_show()
H A Dmmc.c1243 * HS400 mode requires 8-bit bus width in mmc_select_hs400()
1285 pr_err("%s: switch to bus width for hs400 failed, err:%d\n", in mmc_select_hs400()
1290 /* Switch card to HS400 */ in mmc_select_hs400()
1298 pr_err("%s: switch to hs400 failed, err:%d\n", in mmc_select_hs400()
1303 /* Set host controller to HS400 timing and frequency */ in mmc_select_hs400()
1339 /* Switch HS400 to HS DDR */ in mmc_hs400_to_hs200()
1391 /* Prepare tuning for HS400 mode. */ in mmc_hs400_to_hs200()
1491 /* Switch card to HS400 */ in mmc_select_hs400es()
1504 /* Set host controller to HS400 timing and frequency */ in mmc_select_hs400es()
1637 * conditions for HS200 and HS400, which sends CMD21 to the device.
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/
H A Dr8a774e1-hihope-rzg2h.dts40 mmc-hs400-1_8v;

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